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Kimmo Kuusilinna
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2010 – 2019
- 2012
- [c23]Eero Aho, Kimmo Kuusilinna, Tomi Aarnio, Janne Pietiainen, Jari Nikara:
Towards real-time applications in mobile web browsers. ESTIMedia 2012: 57-66
2000 – 2009
- 2009
- [j16]Jarno Vanne
, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen:
A Configurable Motion Estimation Architecture for Block-Matching Algorithms. IEEE Trans. Circuits Syst. Video Technol. 19(4): 466-477 (2009) - [c22]Eero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna:
A case for multi-channel memories in video recording. DATE 2009: 934-939 - [c21]Jari Nikara, Eero Aho, Petri A. Tuominen, Kimmo Kuusilinna:
Performance analysis of multi-channel memories in mobile devices. SoC 2009: 128-131 - [c20]Eero Aho, Kimmo Kuusilinna, Jari Nikara:
Memory access characteristics of H.264 video encoder on embedded processor. SiPS 2009: 255-260 - 2008
- [j15]Jarno Vanne
A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms. IEEE Trans. Circuits Syst. Video Technol. 18(4): 538-543 (2008) - 2007
- [j14]Erno Salminen, Tero Kangas, Vesa Lahtinen, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen:
Benchmarking mesh and hierarchical bus networks in system-on-chip context. J. Syst. Archit. 53(8): 477-488 (2007) - [j13]Eero Aho, Jarno Vanne
Configurable implementation of parallel memory based real-time video downscaler. Microprocess. Microsystems 31(5): 283-292 (2007) - 2006
- [j12]Jarno Vanne
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 16(7): 876-883 (2006) - [j11]Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna:
UML-based multiprocessor SoC design framework. ACM Trans. Embed. Comput. Syst. 5(2): 281-320 (2006) - [j10]Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna:
HIBI Communication Network for System-on-Chip. J. VLSI Signal Process. 43(2-3): 185-205 (2006) - [j9]Tero Kangas, Timo D. Hämäläinen, Kimmo Kuusilinna:
Scalable Architecture for SoC Video Encoders. J. VLSI Signal Process. 44(1-2): 79-95 (2006) - 2005
- [j8]Eero Aho, Jarno Vanne
Block-level parallel processing for scaling evenly divisible images. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(12): 2717-2725 (2005) - [j7]Eero Aho, Jarno Vanne
Comments on "Winscale: an image-scaling algorithm using an area pixel Model". IEEE Trans. Circuits Syst. Video Technol. 15(3): 454-455 (2005) - [c19]Eero Aho, Jarno Vanne
Block-level parallel processing for scaling evenly divisible frames. ISCAS (2) 2005: 1134-1137 - [c18]Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context. SAMOS 2005: 354-363 - 2004
- [j6]Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen:
Address Computation in Configurable Parallel Memory Architecture. IEICE Trans. Inf. Syst. 87-D(7): 1674-1681 (2004) - [c17]Kimmo Kuusilinna, Chen Chang, Hans-Martin Blüthgen, Danijela Cabric, Brian C. Richards, Robert W. Brodersen:
Describing MIMO designs for rapid prototyping in the BEE environment. EUSIPCO 2004: 693-696 - [c16]Jouni Riihimäki, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Practical distributed simulation of a network of wireless terminals. SoC 2004: 49-52 - [c15]Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Comparison of hardware IP components for system-on-chip. SoC 2004: 69-73 - [c14]Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen:
HIBI v.2 Communication Network for System-on-Chip. SAMOS 2004: 413-422 - [c13]Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen:
A Communication-Centric Design Flow for HIBI-Based SoCs. SAMOS 2004: 474-483 - 2003
- [j5]Kimmo Kuusilinna, Chen Chang, M. Josephine Ammer, Brian C. Richards, Robert W. Brodersen:
Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications. EURASIP J. Adv. Signal Process. 2003(6): 502-513 (2003) - [c12]Jouni Riihimäki, Väinö Helminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Distributing SoC Simulations over a Network of Computers. DSD 2003: 447-450 - [c11]Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Robert W. Brodersen:
Implementation of BEE: a real-time large-scale hardware emulation engine. FPGA 2003: 91-99 - [c10]Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Comparison of synthesized bus and crossbar interconnection architectures. ISCAS (5) 2003: 433-436 - [c9]Tero Kangas, Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Using a communication generator in SoC architecture exploration. SoC 2003: 105-108 - [c8]Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Allen Chen, Nathan Chan, Robert W. Brodersen, Borivoje Nikolic
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment. IEEE International Workshop on Rapid System Prototyping 2003: 148- - 2002
- [j4]Kimmo Kuusilinna, Jarno K. Tanskanen, Timo Hämäläinen, Jarkko Niittylahti:
Configurable parallel memory architecture for multimedia computers. J. Syst. Archit. 47(14-15): 1089-1115 (2002) - [j3]Vesa Lahtinen, Kimmo Kuusilinna, Tero Kangas, Timo Hämäläinen:
Interconnection scheme for continuous-media systems-on-a-chip. Microprocess. Microsystems 26(3): 123-138 (2002) - [c7]Jarno Vanne
Enhanced Configurable Parallel Memory Architecture. DSD 2002: 28-37 - [c6]Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo Hämäläinen:
Parameter optimization tool for enhancing on-chip network performance. ISCAS (4) 2002: 61-64 - [c5]Tero Kangas, Kimmo Kuusilinna, Timo Hämäläinen:
TDMA-based communication scheduling in system-on-chip video encoder. ISCAS (1) 2002: 369-372 - [c4]Vesa Lahtinen, Kimmo Kuusilinna, Timo Hämäläinen:
Optimizing finite state machines for system-on-chip communication. ISCAS (1) 2002: 485-488 - 2001
- [c3]Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen:
Interfacing multiple processors in a system-on-chip video encoder. ISCAS (4) 2001: 478-481 - 2000
- [c2]Vesa Lahtinen, Kimmo Kuusilinna, Timo Hämäläinen, Tero Kangas, Jukka Saarinen:
Reuseable interface in multimedia hardware environment. EUSIPCO 2000: 1-4
1990 – 1999
- 1999
- [j2]Kimmo Kuusilinna, Timo Hämäläinen, Jukka Saarinen:
Field programmable gate array-based PCI interface for a coprocessor system. Microprocess. Microsystems 22(7): 373-388 (1999) - [j1]Kimmo Kuusilinna, Timo Hämäläinen, Jukka Saarinen:
Practical VHDL optimization for timing critical FPGA applications. Microprocess. Microsystems 23(8-9): 459-469 (1999) - [c1]Kimmo Kuusilinna, Pasi Liimatainen, Timo Hämäläinen, Jukka Saarinen:
Reconfiguration Mechanism for an IP Block Based Interconnection. EUROMICRO 1999: 1042-1045
Coauthor Index
aka: Timo D. Hämäläinen
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