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Juan José Raygoza-Panduro
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2020 – today
- 2024
- [j8]Emilio Isaac Baungarten-Leon
, Susana Ortega-Cisneros
Vector Accelerator Unit for Caravel. IEEE Embed. Syst. Lett. 16(1): 73-76 (2024) - 2022
- [c11]L. A. Luna-Rodriguez, Francisco J. Rodriguez-Navarrete
Implementation of 8-Channel Pulse Width Modulation with AXI4-Lite Interface. CCE 2022: 1-5
2010 – 2019
- 2019
- [j7]Emmanuel Dávila Delgado
Low cost DSP-based educational embedded platform for real-time simulation and fast implementation of complex systems in Simulink. Comput. Appl. Eng. Educ. 27(4): 955-970 (2019) - 2015
- [j6]Jorge Rivera
FPGA-based startup for AC electric drives: Application to a greenhouse ventilation system. Comput. Ind. 74: 173-185 (2015) - [j5]Susana Ortega-Cisneros
HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision. Computación y Sistemas 19(3) (2015) - [c10]Gerardo Soria García, Adrian Pedroza de-la-Crúz, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Eduardo Bayro-Corrochano:
A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only). FPGA 2015: 272 - [c9]Susana Ortega-Cisneros
Design and implementation of a DC motor control using Field Programmable Analog Arrays. CCE 2015: 1-6 - [c8]Susana Ortega-Cisneros, Jorge Rivera Dominguez
An image processor for convolution and correlation of binary images implemented in FPGA. CCE 2015: 1-5 - 2014
- [j4]Jorge Rivera
Discrete-time modeling and control of a boost converter by means of a variational integrator and sliding modes. J. Frankl. Inst. 351(1): 315-339 (2014) - [c7]Susana Ortega-Cisneros, Miguel A. Carrazco-Díaz, Adrian Pedroza de-la-Crúz, Juan José Raygoza-Panduro, Federico Sandoval-Ibarra, Jorge Rivera Dominguez
Real Time Hardware Accelerator for Image Filtering. CIARP 2014: 80-87 - [c6]J. A. Rentería-Cedano, L. M. Aguilar-Lobo, Susana Ortega-Cisneros
FPGA Implementation of a NARX Network for Modeling Nonlinear Systems. CIARP 2014: 88-95 - [c5]Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Daniel Tonali Aranda Bretón, José Roberto Reyes Barón:
Space-time AER protocol receiver asynchronously controlled on FPGA. CCE 2014: 1-7 - [c4]Susana Ortega-Cisneros
Characterization technique to implement self-timed cells for VLSI design blocks. CCE 2014: 1-6 - 2012
- [j3]Jorge Rivera
Copper and Core Loss Minimization for Induction Motors Using High-Order Sliding-Mode Control. IEEE Trans. Ind. Electron. 59(7): 2877-2889 (2012) - [c3]Alexander G. Loukianov, Jorge Rivera
Super-twisting sensorless control of linear induction motors. CCE 2012: 1-5
2000 – 2009
- 2008
- [j2]Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Jorge Rivera
Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System. Int. J. Reconfigurable Comput. 2008: 634306:1-634306:9 (2008) - 2007
- [j1]Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alberto de la Mora Gálvez:
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs. J. Univers. Comput. Sci. 13(3): 377-387 (2007) - 2005
- [c2]Susana Ortega-Cisneros
Rapid prototyping of a self-timed ALU with FPGAs. ReConFig 2005 - [c1]Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo
FPGA implementation of a synchronous and self-timed neuroprocessor. ReConFig 2005
Coauthor Index
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