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22nd ISCA 1995: Santa Margherita Ligure, Italy
- David A. Patterson:
Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995. ACM 1995, ISBN 0-89791-698-0
Multiprocessors and Applications
- Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David A. Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, Donald Yeung:
The MIT Alewife Machine: Architecture and Performance. 2-13 - Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi:
The EM-X Parallel Computer: Architecture and Basic Performance. 14-23 - Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, Anoop Gupta:
The SPLASH-2 Programs: Characterization and Methodological Considerations. 24-36
Cache Coherence
- Håkan Grahn, Per Stenström:
Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors. 38-47 - Alvin R. Lebeck, David A. Wood:
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors. 48-59 - Fredrik Dahlgren:
Boosting the Performance of Hybrid Snooping Cache Protocols. 60-69
Interconnect Technology and I/O
- Andreas Nowatzyk, Michael C. Browne, Edmund J. Kelly, Michael Parkin:
S-Connect: From Networks of Workstations to Supercomputer Performance. 71-82 - Anujan Varma, Quinn Jacobson:
Destage Algorithms for Disk Arrays with Non-Volatile Caches. 83-95 - Gordon Stoll, Bin Wei, Douglas W. Clark, Edward W. Felten, Kai Li, Pat Hanrahan:
Evaluating Multi-Port Frame Buffer Designs for a Mesh-Connected Multicomputer. 96-105 - Andreas Nowatzyk, Paul R. Prucnal:
Are Crossbars Really Dead? The Case for Optical Multiprocessor Interconnect Systems. 106-115
Instruction Level Parallelism
- Stéphan Jourdan, Pascal Sainrat, Daniel Litaize:
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. 117-125 - Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya:
Unconstrained Speculative Execution with Predicated State Buffering. 126-137 - Scott A. Mahlke, Richard E. Hank, James E. McCormick, David I. August, Wen-mei W. Hwu:
A Comparison of Full and Partial Predicated Execution Support for ILP Processors. 138-150
New Microarchitectures
- Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey:
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. 151-162 - Trung A. Diep, Christopher Nelson, John Paul Shen:
Performance Evaluation of the PowerPC 620 Microarchitecture. 163-175
Managing Memory Hierarchies
- Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, Brian N. Bershad:
Reducing TLB and Memory Overhead Using Online Superpage Promotion. 176-187 - Zheng Zhang, Josep Torrellas:
Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. 188-199
Interconnection Network Routing
- K. V. Anjan, Timothy Mark Pinkston:
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA. 201-210 - Kang G. Shin, Stuart W. Daniel:
Analysis and implementation of hybrid switching. 211-219 - Binh Vien Dao, José Duato, Sudhakar Yalamanchili:
Configurable Flow Control Mechanisms for Fault-Tolerant Routing. 220-229 - Timothy J. Callahan, Seth Copen Goldstein:
NIFDY: A Low Overhead, High Throughput Network Interface. 230-241
Novel Memory Access Mechanisms
- Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang:
Vector Multiprocessors with Arbitrated Memory Access. 243-252 - Krishna M. Kavi, Ali R. Hurson
, Phenil Patadia, Elizabeth Abraham, Ponnarasu Shanmugam:
Design of Cache Memories for Multi-Threaded Dataflow Architecture. 253-264 - François Bodin, André Seznec:
Skewed Associativity Enhances Performance Predictability. 265-274
Branch Prediction
- Cliff Young, Nicholas C. Gloy, Michael D. Smith:
A Comparative Analysis of Schemes for Correlated Branch Prediction. 276-286 - Brad Calder, Dirk Grunwald:
Next Cache Line and Set Prediction. 287-296
System Evaluation
- Vijay Karamcheti, Andrew A. Chien:
A Comparison of Architectural Support for Messaging in the TMC CM-5 and the Cray T3D. 298-307 - Thomas Stricker, Thomas R. Gross:
Optimizing Memory System Performance for Communication in Parallel Computers. 308-319 - Remzi H. Arpaci, David E. Culler, Arvind Krishnamurthy, Steve G. Steinberg, Katherine A. Yelick:
Empirical Evaluation of the CRAY-T3D: A Compiler Perspective. 320-331
Instruction Fetching
- Thomas M. Conte
Optimization of Instruction Fetch Mechanisms for High Issue Rates. 333-344 - Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer:
Instruction Fetching: Coping with Code Bloat. 345-356 - Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald:
Instruction Cache Fetch Policies for Speculative Execution. 357-367
Caches
- Todd M. Austin, Dionisios N. Pnevmatikatos
Streamlining Data Cache Access with Fast Address Calculation. 369-380 - Hong Wang, Tong Sun, Qing Yang:
CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. 381-390
Processor Architecture
- Dean M. Tullsen, Susan J. Eggers, Henry M. Levy:
Simultaneous Multithreading: Maximizing On-Chip Parallelism. 392-403 - Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill:
Architecture Validation for Processors. 404-413 - Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar:
Multiscalar Processors. 414-425
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