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48th ESSCIRC 2022: Milan, Italy
- 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022, Milan, Italy, September 19-22, 2022. IEEE 2022, ISBN 978-1-6654-8494-7
- Davide Tonietto:
The Future of Short Reach Interconnect. 1-8 - Tim Gutheit:
Semiconductors take the driver's seat - challenges and opportunities for the car of the future. 9-11 - Dirk Droste, Horst Symanzik, Timo Gießelmann, Markus Ulm, Ivano Galdi, Riccardo Campagna:
Integrated Circuits as Key Enabler for today's Smart MEMS Sensors. 12-16 - Domenico Arrigo, Claudio Adragna
, Vincenzo Marano, Rachela Pozzi, Fulvio Pulicelli, Francesco Pulvirenti:
The Next "Automation Age": How Semiconductor Technologies Are Changing Industrial Systems and Applications. 17-24 - Rinaldo Castello:
Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz. 25-32 - Massimo Alioto:
From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs. 33-40 - Vida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De:
Innovations for Intelligent Edge. 41-44 - Bruna Cardoso Paz, Victor El-Homsy, David J. Niegemann, Bernhard Klemt, Emmanuel Chanrion, Vivien Thiney, Baptiste Jadot, Pierre-André Mortemousque, Benoit Bertrand, Thomas Bedecarrats, Heimanu Niebojewski, François Perruchot, Silvano De Franceschi, Maud Vinet, Matias Urdampilleta, Tristan Meunier:
Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology. 45-48 - Fabio Bersano, Franco De Palma, Fabian Oppliger, Floris Braakman, Ionut Radu
Multi-Gate FD-SOI Single Electron Transistor for hybrid SET-MOSFET quantum computing. 49-52 - Gerd Kiene, Aishwarya Gunaputi Sreenivasulu, Ramon Overwater
Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC. 53-56 - Mridula Prathapan, Peter Mueller
A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control. 57-60 - Steven Van Winckel
A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout. 61-64 - Mohammad Ayaz Masud, Luis Hurtado, Gianluca Piazza
Non-Volatile Ternary Content Addressable Memory based on Phase Change Nanoelectromechanical (NEM) Relay. 65-68 - Jonas Pelgrims, Kris Myny
A 24V Thin-Film Ultrasonic Driver for Haptic Feedback in Metal-Oxide Thin-Film Technology using Hybrid DLL Locking Architecture. 69-72 - Nicola Massari, Alessandro Tontini, Luca Parmesan, Matteo Perenzoni, Milos Grujic
A monolithic SPAD-based random number generator for cryptographic application. 73-76 - Danielius Kramnik, Imbert Wang, Josep M. Fargas Cabanillas, Anirudh Ramesh
Quantum-Correlated Photon-Pair Source with Integrated Feedback Control in 45 nm CMOS. 77-80 - Yu-Chun Ding, Kai-Pin Lin, Chi-Wen Weng, Li-Wei Wang, Huan-Ching Wang, Chun-Yeh Lin, Yong-Tai Chen, Chao-Tsung Huang:
A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps. 81-84 - Seong Hoon Seo
A 40nm 5.6TOPS/W 239GOPS/mm2 Self-Attention Processor with Sign Random Projection-based Approximation. 85-88 - Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. 89-92 - Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu:
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement. 93-96 - Sumin Lee, Ki-Beom Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee
SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution. 97-100 - Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling. 101-104 - Geethan Karunaratne, Michael Hersche, Jovin Langenegger, Giovanni Cherubini, Manuel Le Gallo, Urs Egger, Kevin Brew, Samuel Choi, Injo Ok, Mary Claire Silvestre, Ning Li, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory. 105-108 - Alessio Antolini
An embedded PCM Peripheral Unit adding Analog MAC In-Memory Computing Feature addressing Non-linearity and Time Drift Compensation. 109-112 - Sehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Minki Kim, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung:
A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF. 113-116 - Manuel Escudero, Sabina Spiga
Physical Implementation of a Tunable Memristor-based Chua's Circuit. 117-120 - Fengben Xi
Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing. 121-124 - Justine Barbot, Jean Coignus
Interplay between charge trapping and polarization switching in MFDM stacks evidenced by frequency-dependent measurements. 125-128 - Ahmed Trabelsi, Carlo Cagli, Tifenn Hirtzlin, Olga Cueto, Marie Claire Cyrille, Elisa Vianello, Valentina Meli, Veronique Sousa, Guillaume Bourgeois, François Andrieu:
Frequency modulation of conductance level in PCM device for neuromorphic applications. 129-132 - Alessandro Milozzi, Daniel Reiser, Andreas Drost, Thomas Neuner, Marc Tornow, Daniele Ielmini:
Thermal switching of TiO2-based RRAM for parameter extraction and neuromorphic engineering. 133-136 - Suzanne Lancaster, Quang T. Duong, Erika Covi
Improvement of FTJ on-current by work function engineering for massive parallel neuromorphic computing. 137-140 - Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon:
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training. 145-148 - Jie Lou, Christian Lanius, Florian Freye, Tim Stadtmann, Tobias Gemmeke
All-Digital Time-Domain Compute-in-Memory Engine for Binary Neural Networks With 1.05 POPS/W Energy Efficiency. 149-152 - Amitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang
A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. 153-156 - Adrian Kneip
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization. 157-160 - Sadegh Kamaei, Ali Saeidi, Xia Liu, Carlotta Gastaldi, Clara Moldovan, Jürgen Brugger, Adrian M. Ionescu:
Fully integrated Si: HfO2 Negative Capacitance 2D-2D WSe2/SnSe2 Subthermionic Tunnel FETs. 161-164 - Lukas Seidel, Sören Schäfer, Michael Oehme, Dan Buca, Giovanni Capellini
Electroluminescence of SixGe1-x-ySny/Ge1-ySny pin-Diodes Grown on a GeSn Buffer. 165-168 - Maurice Wanitzek
GeSn-on-Si Avalanche Photodiodes for Short-Wave Infrared Detection. 169-172 - Jui-Hung Sun
A Drift-Compensated Magnetic Spectrometer for Point-of-Care Wash-Free Immunoassays using a Concurrent Dual-Frequency Oscillator. 173-176 - Edgar F. M. Albuquerque, Ricardo Bugalho, Luís B. Oliveira
A Full Current-Mode Timing Circuit with Dark Noise Suppression for the CERN CMS Experiment. 177-180 - Yuting Shen, Mariska van der Struijk, Kevin Pelzers, Hanyue Li, Eugenio Cantatore, Pieter Harpe:
A 2.74pJ/conversion 0.0018mm2 Temperature Sensor with On-chip Gain and Offset Correction. 181-184 - Alexander Frank, Jens Anders, Joachim N. Burghartz, Bart Kootte, Jean Schleipen, Peter Jutte:
An Integrated Optical Transceiver Circuit for Power Delivery and Bi-directional Data Communication in a Medical Catheter Device. 185-188 - Leonardo Gasparini
A reconfigurable 224×272-pixel single-photon image sensor for photon timestamping, counting and binary imaging at 30.0-μm pitch in 11 0nm CIS technology. 189-192 - Mathieu Sicre, Megan Agnew, Christel Buj, Caroline Coutier, Dominique Golanski, Rémi Helleboid, Bastien Mamdy, Isobel Nicholson, Sara Pellegrini, Denis Rideau, David Roy, Françis Calmon:
Statistical measurements and Monte-Carlo simulations of DCR in SPADs. 193-196 - Nicola Massari, Alessio D'Andragora, Matteo Perenzoni, Andrey Selijak, Carlos Chavez Barajas, Alan Taylor, Jon Taylor, Gianluigi Casse
A scalable 64×64 pixels monolithic HV-CMOS sensor for hadron therapy with 1ns time stamping capability and in-pixel ADC. 197-200 - Stefan Reich, Markus Sporer, Joachim Becker, Stefan B. Rieger, Martin Schüttler, Maurits Ortmanns:
A 32-ch Neuromodulator with redundant Voltage Monitors avoiding Blocking Capacitors. 201-204 - Eric H. Pollmann
Fully Implantable 192×256 SPAD Sensor with Global-Shutter and Micro-LEDs for Bidirectional Subdural Optical Brain-Computer Interfaces. 205-208 - Baibhab Chatterjee
A 1.8 μW 5.5 mm3 ADC-less Neural Implant SoC utilizing 13.2pJ/Sample Time-domain Bi-phasic Quasi-static Brain Communication with Direct Analog to Time Conversion. 209-212 - Jaehyun Ko, Iksu Jang
A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec. 213-216 - Oi-Ying Wong, Dries Tabruyn, Veronique Rochus, Nick Van Helleputte:
An Implantable Power Extraction Circuit with Integrated PMUTs for Wireless Power Delivery. 217-220 - Lara Novaresi, Piero Malcovati, Andrea Mazzanti, Edoardo Bonizzoni, Marco Terenzi, Stefano Ottaviani, Davide Ghisu, Fabio Quaglia, Alessandro Stuart Savoia
A PMUT Transceiver Front-End with 100-V TX Driver and Low-Noise Voltage Amplifier in BCD-SOI Technology. 221-224 - Daniel Krüger, Aoyang Zhang, Henry Hinton, Victor Marrugat Arnal, Yi-Qiao Song, Yiqiao Tang, Ka-Meng Lei, Jens Anders, Donhee Ham:
A Portable CMOS-based MRI System with 67×67×83 µm3Image Resolution. 225-228 - Cheng Chen, Zhouchen Ma, Yaxin Liu, Zhenhong Liu, Linfeng Zhou, Yan Wu, Liang Qi, Yongfu Li, Mohamad Sawan, Guoxing Wang, Jian Zhao:
A Sub-0.01° Phase Resolution 6.8-mW fNIRS Readout Circuit Employing a Mixer-First Frequency-Domain Architecture. 229-232 - Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi:
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv. 233-236 - Staffan Ek, Patrik Karlsson, Andreas Kämpe, Roland Strandberg, Aravind Tharayil Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, Nikola Ivanisevic, Robert Nilsson, Peter Nygren, Mattias Palm, Erik Säll, Sha Tao, My-Chien Yee, Lars Sundström
A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology. 237-240 - Dong-Hyun Yoon, Kwang-Hyun Baek
A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process. 241-244 - Masaru Osada, Zule Xu, Tetsuya Iizuka:
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. 245-248 - Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong:
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. 249-252 - Shubham Mehrotra, Efraïm Eland, Shoubhik Karmakar, Angqi Liu, Burak Gönen, Muhammed Bolatkale, Robert H. M. van Veldhoven, Kofi A. A. Makinwa:
A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC. 253-256 - Alessandro Catania, Andrea Ria, Giuseppe Manfredini, Michele Dei, Massimo Piotto, Paolo Bruschi:
A 150 mV, Sub-1 nW, 0.75%-Full-Scale INL Delta-Sigma ADC for Power-Autonomous Sensor Nodes. 257-260 - Jonah Van Assche, Georges G. E. Gielen:
A 10.4-ENOB 0.92-5.38 μW Event-Driven Level-Crossing ADC with Adaptive Clocking for Time-Sparse Edge Applications. 261-264 - Jens Karrenbauer
SmartHeaP - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI. 265-268 - Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose:
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. 269-272 - Angelo Garofalo, Matteo Perotti, Luca Valente
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. 273-276 - Peng Cao
A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages. 277-280 - Jin Woong Kwak, Dongsheng Brian Ma:
An Automotive-Use Dual-fsw-Zone Hybrid Switching Power Converter with Vo-Jitter-Immune Spread-Spectrum Modulation. 281-284 - Wei-Cheng Huang, Yuan-Jin Li, Yi-Hsiang Kao, Ke-Horng Chen
A Galvanic-Free Secondary-Side Control Flyback Converter with Digital Adaptive On-Time Control and Direct Sequence Spread Spectrum Technique for 15.5% Error Recovery Rate Improvement. 285-288 - Michael Hanhart, Jonas Zoche, Jan Grobe
A Half-Bridge Gate-Driver for high-efficient Boost Converter Applications with single-sided ZVS and an adaptive Ringing Suppression Technique. 289-292 - Si-Yi Li, Zheng-Lun Huang, Sheng Cheng Lee, Ke-Horng Chen
A 4 to 40V Wide Input Range and Energy Re-Cycling High Power LiDAR Driver for 5% Efficiency Enhancement and 300m Long-distance Object Detection. 293-296 - Valentyn Solomko, Semen Syroiezhin, Danial Tayari, Jochen Essel, Robert Weigel:
High-Voltage CMOS RF Switch with Active Biasing. 297-300 - Semen Syroiezhin, Oguzhan Oezdamar, Robert Weigel, Valentyn Solomko:
Switching Time Acceleration for High-Voltage CMOS RF Switch. 301-304 - Alexandre Flete, Christophe Viallon, Philippe Cathelin, Thierry Parra:
A Low-Loss 77 GHz Sub-Sampling Passive Mixer Integrated in a 28-nm CMOS Radar Receiver. 305-308 - Jin Jin, Simone Lecchi, Rinaldo Castello, Danilo Manstretta:
An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier. 309-312 - Jing-Siang Chen, Chun-Ting Chang, Yu-Te Liao
A 433-MHz Wireless Burst-Chirp Modulation Transmitter with Adaptive Duty-Cycle Control and Precharge Mechanism. 313-316 - Woojin Jang
A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity. 317-320 - Pierluigi Cenci, Hans Brekelmans, Shagun Bajoria, Marcello Ganzerli, Bernard Burdiek, Robert Rutten, Yihan Gao, Muhammed Bolatkale, Paul Swinkels, Lucien J. Breems:
A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW. 321-324 - Evelyn Ware, Justin M. Correll
6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration. 325-328 - Pietro Caragiulo, Athanasios Ramkaj, Amin Arbabian, Boris Murmann:
A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS. 329-332 - Minzhe Tang, Yi Zhang, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio. 333-336 - Hao Gao, Sina Mortezazadeh Mahani, David Seebacher, Matteo Bassi, Gernot Hueber:
A 24-30 GHz Broadband Doherty PA with a maximum 15.37 dBm Pavg and 14.6% PAEavg in 0.13 μm SiGe for 400 MHz BW 5G NR. 337-340 - Kyutaek Oh, Hyunjin Ahn, Ilku Nam, Ockgoo Lee:
A 24-to-44 GHz Compact Linear 5G Power Amplifier with Open-Terminated Balun in 65nm Bulk CMOS. 341-344 - Sena Kato, Keito Yuasa, Michihiro Ide, Atsushi Shirane, Kenichi Okada:
A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay Transceivers. 345-348 - Paul Xuanyuanliang Huang, Daniel Jang, Yannis P. Tsividis, Mingoo Seok:
INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential Equations. 349-352 - Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim:
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method. 353-356 - Oscar Castañeda, Luca Benini, Christoph Studer:
A 283 pJ/b 240 Mb/s Floating-Point Baseband Accelerator for Massive MU-MIMO in 22FDX. 357-360 - Jing-Ren Yan, Hao-Yi Kuo, Yu-Te Liao
A Wide-input-range 918MHz RF Energy Harvesting IC with Adaptive Load and Input Power Tracking Technique. 361-364 - Shu-Yung Lin, Sheng Cheng Lee, Ke-Horng Chen
Input Nonlinear Adaptive Voltage Position Technique in the Switched-capacitor Converter with Feedforward Compensation for 87.8% Peak Efficiency under 8X Input Interference. 365-368 - Omer Nechushtan, Asaf Feldman
A 385mV, 270nW, Accurate Voltage Level Detector for IoT. 369-372 - Marcella Carissimi, Chantal Auricchio, Emanuela Calvetti, Laura Capecchi, Mattia Luigi Torres, Stefano Zanchi, P. Gupta, Riccardo Zurla, Alessandro Cabrini, Daniele Gallinari, Fabio Disegni, Massimo Borghi, Elisabetta Palumbo, Andrea Redaelli
An Extended Temperature Range ePCM Memory in 90-nm BCD for Smart Power Applications. 373-376 - Amit Agarwal, Steven Hsu, Mark A. Anders, Gunjan Pandya, Ram Krishnamurthy, James W. Tschanz, Vivek De:
On-Chip High-Resolution Timing Characterization Circuits for Memory IPs. 377-380 - Orazio Aiello, Massimo Alioto:
Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting. 381-384 - Agata Iesurum
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS. 385-388 - Lorenzo Piotto
A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology. 389-392 - Yudai Yamazaki, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 1.8-67GHz Divide-by-4 ILFD Using Area-Efficient Transformer-Based Injection-Enhancing Technique. 393-396 - Wim Kruiskamp:
A Fully Differential 40 MHz Switched-Capacitor Crystal Oscillator with Fast Start-Up. 397-400 - Gerard Mora-Puchalt, Gabriel Banarie, Pawel Czapor, Adrian Sherry, Roberto Maurino, Jesús Bonache, Italo Medina:
A 128ksps 120dB THD Low Noise Analog Front End. 401-404 - Paolo Crovetti, Roberto Rubino, Pedro Toledo, Francesco Musolino, Hamilton Klimach, Yong Chen, Anna Richelli:
A 0.01mm2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification. 405-408 - Jose Luis Ceballos, Christopher Rogi, Fulvio Ciciotti, Cesare Buffa, Dietmar Straeussnigg, Andreas Wiesbauer:
A 69dBA-730µW Silicon Microphone System with Ultra & Infra-Sound Robustness. 409-412 - Ian Costanzo, Devdip Sen, John A. McNeill
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements. 413-416 - Xichen Li
A 2.4GHz Full-Duplex Transceiver with Broadband (+120MHz), Linearity-Calibrated and Long-Delayed Self-Interference Cancellation. 417-420 - Elbert Bechthum, Minyoung Song
A 3-10GHz 21.5mW/Channel RX and 8.9mW TX IR-UWB 802.15.4a/z 1T3R Transceiver. 421-424 - Nicola Cordioli, Danilo Manstretta, Rinaldo Castello:
A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology. 429-432 - Peizhuo Wang, Tianxiang Qu
A 136GΩ-Input-Impedance Active Electrode for Non-Contact ECG Using Auto-Calibrated Positive Feedback and Capacitance Scaling in Femtofarad Resolution. 433-436 - Surachoke Thanapitak, Chutham Sawigun:
A Chopper Biopotential Instrumentation Amplifier With DSL-Embedded Input Stage Achieving 109 dB CMRR and 400 mV DC Offset Tolerance. 437-440 - Yingjie Chen
A Direct Sensor Readout Circuit Using VCO-Driven Chopping with 42dB SNR at 800µVpp Input. 441-444 - Rémi Dekimpe
Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End. 445-448 - Tim Maiwald, Akshay Visweswaran, Klaus Aufinger, Robert Weigel:
A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation. 449-452 - Jeff Shih-Chieh Chien, James F. Buckwalter:
A 111-149-GHz, Compact Power-combined Amplifier With 17.5-dBm Psat, 16.5% PAE in 22-nm CMOS FD-SOI. 453-456 - Gabriel Guimaraes, Patrick Reynaert:
A D-Band mm-wave spectroscopy TX and RX in 28 nm CMOS with 15.6 dBm EIRP and 17.1 dB NF with integrated antennas. 457-460 - Hossein Jalili, Yuqi Liu, Tzu-Yuan Huang, Hua Wang:
A Joint Space/Time Modulation Lens-Coupled 230-GHz Terahertz Source with 40°/43°2-D Beam Steering for Fast High-Resolution Imaging/Sensing Applications. 461-464 - Martin Lefebvre
A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI. 469-472 - Antonio Aprile
A Compact 2.5-nJ Energy/Conversion NPN-Based Temperature-to-Digital Converter with a Fully Current-Mode Processing Architecture. 473-476 - Liangbo Lei, Cong Tao, Zhipeng Chen, Zhiliang Hong, Yumei Huang:
A 5.4-mW 50-MHz 29.3-dBm-IIP3 Fourth-Order Low-Pass Filter. 477-480 - Carl D'heer
A 135 GHz 32 Gb/s Direct-Digital Modulation 16-QAM Transmitter in 28 nm CMOS. 481-484 - Carl D'heer
A 135 GHz 24 Gb/s Direct-Digital Demodulation 16-QAM Receiver in 28 nm CMOS. 485-488 - Ethan Chou
A Low-Power and Energy-Efficient D-Band CMOS Four-Channel Receiver with Integrated LO Generation for Digital Beamforming Arrays. 489-492 - Deniz Dosluoglu
A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver. 493-496 - Xiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong
A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. 497-500 - Liping Zhong
A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS. 501-504 - Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi:
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. 505-508 - Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET. 509-512 - Kunyang Liu
A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance. 513-516 - Beomsoo Park, Nima Mazhari:
A 183F2 Gate Leakage-Based Physically Unclonable Function With Area Efficient Current Tilting-Based Masking Scheme. 517-520 - Seonho Kim
Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security. 521-524 - ByungJun Kim, Jaehan Park, Seunghyun Moon
Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Devices. 525-528 - Meizhi Wang
Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks. 529-532 - Farshid Ashtiani, Firooz Aflatouni:
Integrated Optical Phased Arrays on Silicon. 538-541 - Hany Abolmagd, Raghav Subbaraman, Dinesh Bharadia, Sudip Shekhar:
Full-Duplex Wireless for (Joint-) Communication and Sensing. 542-545 - Kaushik Sengupta
Reconfigurable Intelligent Surfaces Enabled by Silicon Chips for Secure and Robust mmWave and THz Wireless Communication. 546-549 - Lairong Fang
A 130μW Three-Step DT Incremental Δ ∑ ADC Achieving 107.6dB DR and 99.3dB SNDR with Zoom and Extended-Range Counting. 554-557 - Morteza Tavakoli Taba, S. M. Hossein Naghavi
A Review on the State-of-the-Art THz FMCW Radars Implemented on Silicon: Invited. 533-537
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