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EURO-DAC 1994: Grenoble, France
- Jean Mermet:
Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994. IEEE Computer Society 1994, ISBN 0-89791-685-9 - Rolf Drechsler, Bernd Becker, Michael Theobald:
Fast OFDD based minimization of fixed polarity Reed-Muller expressions. 2-7 - Marek A. Perkowski, Philip Ho:
Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping. 8-13 - Luc Burgun, N. Dictus, Alain Greiner, E. Prado Lopes, C. Sarwary:
Multilevel logic optimization of very high complexity circuits. 14-19 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Symbolic exploration of large circuits with enhanced forward/backward traversals. 22-27 - Stefan Lenk:
Extended timing diagrams as a specification language. 28-33 - Ti-Yen Yen, Wayne H. Wolf, Albert E. Casavant, Alex Ishii:
Efficient algorithms for interface timing verification. 34-39 - Kerry S. Lowe, P. Glenn Gulak:
A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits. 42-47 - Markus Theißinger, Ronald D. Hindmarsh:
Layout optimization of planar CMOS cells regarding width-to-height trade-off. 48-53 - Hervé Mathias, Josette Berger-Toussan, Frédéric Gaffiot, L. Hébrard, Gilles Jacquemod, Michel Le Helley:
Automatic layout generation for CMOS analog transistors. 54-58 - Klaus Buchenrieder, Christian Veith:
A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA's. 60-65 - Jie Gong, Daniel D. Gajski, Alex Nicolau:
A performance evaluator for parameterized ASIC architectures. 66-71 - A. Both, B. Biermann, R. Lerch, Yiannos Manoli, K. Sievert:
Hardware-software-codesign of application specific microcontrollers with the ASM environment. 72-76 - Marc Wendling, Wolfgang Rosenstiel:
A hardware environment for prototyping and partitioning based on multiple FPGAs. 77-82 - Ali Shahid, Muhammad S. T. Benten, Sadiq M. Sait:
GSA: scheduling and allocation using genetic algorithm. 84-89 - Birger Landwehr, Peter Marwedel, Rainer Dömer:
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming. 90-95 - Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul, Marian Adamski:
Parallel controller synthesis from a Petri net specification. 96-101 - Werner Rissiek, O. Rethmeier, Heike Holzheuer:
Parallel algorithms for the simulation of lossy transmission lines. 104-109 - Konstantin O. Petrosjanc, Peter P. Maltcev:
Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpice. 110-115 - Matthias Tröscher, Hans Hartmann, Georg Klein, Andreas Plettner:
TRICAP - a three dimensional capacitance solver for arbitrarily shaped conductors on printed circuit boards and VLSI interconnections. 116-121 - S. Forno, Stephen Rochel:
Advanced simulation and modeling techniques for hardware quality verification of digital systems. 122-127 - James B. Burr, Allen M. Peterson, Gerard K. Yeh, Kallol Kumar Bagchi:
OPERAS in a DSP CAD environment. 130-135 - Kaushik Roy, Sharat Prasad:
Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects. 136-141 - Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung:
100-hour design cycle: a test case. 144-149 - Bruce K. Holmer:
A tool for processor instruction set design. 150-155 - Peter Marwedel, Rainer Leupers:
Instruction set extraction from programmable structures. 156-161 - Sudhakar Muddu, Andrew B. Kahng:
Optimal equivalent circuits for interconnect delay calculations using moments. 164-169 - Peter Feldmann, Roland W. Freund:
Efficient linear circuit analysis by Padé approximation via the Lanczos process. 170-175 - Vladimir B. Dmitriyev-Zdorov:
Multilevel generalization of relaxation algorithms for circuit simulation. 176-181 - Victor V. Denisenko:
MOS VLSI circuit simulation by hardware accelerator using semi-natural models. 182-186 - A. J. van der Hoeven, K. Olav ten Bosch, Rene van Leuken, Pieter van der Wolf:
A flexible access control mechanism for CAD frameworks. 188-193 - Flávio Rech Wagner, Lia Goldstein Golendziner, Miguel Rodrigues Fornari:
A tightly coupled approach to design and data management. 194-199 - Nick Filer, Michael Brown, Zahir Moosa:
Integrating CAD tools into a framework environment using a flexible and adaptable procedural interface. 200-205 - Olav Schettler:
Design tool encapsulation - all problems solved? 206-211 - Frank Vahid, Daniel D. Gajski, Jie Gong:
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. 214-219 - Xun Xiong, Edna Barros, Wolfgang Rosenstiel:
A method for partitioning UNITY language in hardware and software. 220-225 - Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen:
Hardware/software partitioning and minimizing memory interface traffic. 226-231 - Edgar Holmann, Ivan R. Linscott, G. Leonard Tyler:
Reliability study of combinatorial circuits. 234-239 - Arno Kunzmann:
Test pattern generation hardware motivated by pseudo-exhaustive test techniques. 240-245 - Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda:
An experimental analysis of the effectiveness of the circular self-test path technique. 246-251 - Sayed Mohammad Kia, Sri Parameswaran:
Design automation of self checking circuits. 252-257 - Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
An architecture-independent approach to FPGA routing based on multi-weighted graphs. 259-264 - Shashidhar Thakur, D. F. Wong
, S. Muthukrishnan:
Algorithms for a switch module routing problem. 265-270 - Roman Kuznar, Baldomir Zajc, Franc Brglez:
A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. 271-276 - Srilata Raman, C. L. Liu, Larry G. Jones:
A delay driven FPGA placement algorithm. 277-282 - Ramayya Kumar, Sofiène Tahar:
Formal verification of pipeline conflicts in RISC processors. 284-289 - Matthias Mutz:
An automatically verified generalized multifunction arithmetic pipeline. 290-295 - Edwin A. Harcourt, Jon Mauney, Todd A. Cook:
Formal specification and simulation of instruction-level parallelism. 296-301 - Krzysztof Bilinski, Erik L. Dagless, Jonathan Saul, Janusz Szajna:
An efficient verification algorithm for parallel controllers. 302-307 - Andrzej Krasniewski, Leszek B. Wronski:
Tests for path delay faults vs. tests for gate delay faults: how different they are. 310-315 - Karl Fuchs, Michael Pabst, Torsten Rössel:
RESIST: a recursive test pattern generation algorithm for path delay faults. 316-321 - Rolf Drechsler:
BiTeS: a BDD based test pattern generator for strong robust path delay faults. 322-327 - Luciano Lavagno, Antonio Lioy, Michael Kishinevsky:
Testing redundant asynchronous circuits by variable phase splitting. 328-333 - Salvador Mir, Nick Filer:
Re-engineering hardware specifications by exploiting design semantics. 336-341 - Michael Brown, Nick Filer, Zahir Moosa:
The use of semantic information for control of a complex routing tool. 342-347 - Félix Moreno, Juan M. Meneses:
A new knowledge-based design manager assistant for CAD frameworks. 348-353 - Chris J. Rousse, Alison J. Carter:
The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithm. 354-359 - Winfried Hahn, Andreas Hagerer, C. Herrmann:
Compiled-code-based simulation with timing verification. 362-367 - Peter Luksch:
A portable and extendible testbed for distributed logic simulation. 368-373 - Jindrich Zejda, Eduard Cerny:
Gate-level timing verification using waveform narrowing. 374-379 - Rafael Peset Llopis:
Exact path sensitization in timing analysis. 380-385 - Peter H. Schneider, Kurt Antreich, Ulf Schlichtmann:
A new power estimation technique with application to decomposition of Boolean functions for low power. 388-393 - C. Y. Roger Chen, Mohammed Aloqeely:
A new technique for exploiting regularity in data path synthesis. 394-399 - Smita Bakshi, Daniel D. Gajski:
A component selection algorithm for high-performance pipelines. 400-405 - E. Griese, J. Schrage, M. Vogt:
Fast simulation method for the detection of reflection - and crosstalk effects during the design of complex printed circuit boards. 408-413 - Stefan Öing, Werner John:
Design support of printed circuit boards concerning radiation and irradiation effects (EMI): using an extended EMC-Workbench. 414-419 - Jean-Louis Blanchard, Jean-Michel Morelle:
Overall thermal simulation of electronic equipment. 420-425 - Henrik Esbensen:
A macro-cell global router based on two genetic algorithms. 428-433 - Zahir Moosa, Michael Brown, Douglas Edwards:
An appreciation of simulated annealing to maze routing. 434-439 - Chung-Wen Albert Tsao, Andrew B. Kahng:
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. 440-445 - Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekbergen:
A general state graph transformation framework for asynchronous synthesis. 448-453 - Christian D. Nielsen:
Evaluation of function blocks for asynchronous design. 454-459 - Reimund Wittmann, Bedrich J. Hosticka, Michael Schanz, Werner Schardein, Stefan Kern, Reinhold Vahrmann:
Application-independent hierarchical synthesis methodology for analogue circuits. 466-471 - Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik, Alexander J. Honcharik:
Generating VHDL models from natural language descriptions. 474-479 - Kevin O'Brien, Serge Maginot:
Non-reversible VHDL source-source encryption. 480-485 - Jan Madsen, Jens P. Brage:
Modeling shared variables in VHDL. 486-491 - Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuominen:
A VHDL-based bus model for multi-PCB system design. 492-497 - Wolfgang Müller, Egon Börger, Uwe Glässer:
The semantics of behavioral VHDL '93 descriptions. 500-505 - Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto:
A process algebra interpretation of a verification oriented overlanguage of VHDL. 506-511 - Luis Sánchez Fernández, Peter T. Breuer, Carlos Delgado Kloos:
Proof theory and a validation condition generator for VHDL. 512-517 - Juan Carlos Calderón, Enric Corominas, José M. Tapia, Luis París:
Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools. 520-525 - France Mendez:
VHDL and cyclic corrector codes. 526-531 - Michael Held, Manfred Glesner:
Generating compilers for generated datapaths. 532-537 - Petru Eles, Marius Minea, Krzysztof Kuchcinski, Zebo Peng:
Synthesis of VHDL concurrent processes. 540-545 - Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler:
Scheduling of behavioral VHDL by retiming techniques. 546-551 - Frank Vahid, Daniel D. Gajski, Sanjiv Narayan:
A transformation for integrating VHDL behavioral specification with synthesis and software generation. 552-557 - Felix Nicoli, Laurence Pierre:
Formal verification of behavioral VHDL specifications: a case study. 560-565 - Hans Eveking:
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems. 566-571 - Gert Döhmen:
Petri nets as intermediate representation between VHDL and symbolic transition systems. 572-577 - Ronald Herrmann, Hergen Pargmann:
Computing binary decision diagrams for VHDL data types. 578-583 - Mario Stefanoni:
Static analysis for VHDL model evaluation. 586-591 - Karen Hale:
Automotive databus simulation using VHDL. 592-597 - David B. Bernstein, Werner van Almsick, Wilfried Daehn:
Distributed simulation for structural VHDL netlists. 598-603 - Arlet Ottens, Henk Corporaal, Wilco Van Hoogstraeten:
A new flexible VHDL simulator. 604-609 - Donatella Sciuto, Stefano Antoniazzi, Alessandro Balboni, William Fornaciari:
The role of VHDL within the TOSCA hardware/software codesign framework. 612-617 - Peter Gutberlet, Wolfgang Rosenstiel:
Timing preserving interface transformations for the synthesis of behavioral VHDL. 618-623 - Wolfgang Ecker, Manfred Glesner, Andreas Vombach:
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. 624-629 - Loïc Vandeventer, Jean François Santucci:
Speeding up test pattern generation from behavioral VHDL descriptions containing several processes. 632-637 - Loïc Vandeventer, Jean François Santucci:
Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructs. 638-643 - Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
Testability analysis and improvement from VHDL behavioral specifications. 644-649 - Christopher A. Ryan, Joseph G. Tront:
VHDL switch level fault simulation. 650-655 - Koen Van Nieuwenhove, Kjell Cools, D. Devisch, Ivo Bolsens, Serge Vernalde, Kim Chansik, R. B. W. Lee, Oh Younguk:
ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon Codec. 658-663 - Maurizio Valle, Daniele D. Caviglia, Marco Cornero, Giovanni Nateri, Luciano Briozzo:
A VHDL-based design methodology: the design experience of a high performance ASIC chip. 664-669 - Daniel Clavelier, Bernard Hennion, Christopher Nilson:
SYNOPA: an automated synthesizer for CMOS operational amplifiers. 670-675 - Alain Greiner, Frédéric Pétrot:
Using C to write portable CMOS VLSI module generators. 676-681 - Stefan Tamme:
Rapid prototyping for DSP circuits using high level design tools. 682-687 - Alexander Y. Tetelbaum:
CAD education and science in Ukraine after Perestroika. 688-693
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