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Gate-level timing verification using waveform narrowing

Authors:

Jindrich Zejda,

Eduard CernyAuthors Info & Claims

EURO-DAC '94: Proceedings of the conference on European design automation

Pages 374 - 379

Published: 23 September 1994 Publication History

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References

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Cited By

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Sakamoto TYamada TMukuno MMatsushita YHarada YYasuura HDe VIrwin MVerbauwhede IPiguet C(2002)Power analysis techniques for SoC with improved wiring modelsProceedings of the 2002 international symposium on Low power electronics and design10.1145/566408.566476(259-262)Online publication date: 12-Aug-2002
https://dl.acm.org/doi/10.1145/566408.566476
Kassab MCerny EAourid SKrodel TDewilde PRammig FMusgrave G(1998)Propagation of last-transition-time constraints in gate-level timing analysisProceedings of the conference on Design, automation and test in Europe10.5555/368058.368418(796-802)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368418
Zejda JCerny EShenoy SRumin N(1996)Bounding Switching Activity in CMOS Circuits Using Constraint ResolutionProceedings of the 1996 European conference on Design and Test10.5555/787259.787624Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787624

Index Terms

Gate-level timing verification using waveform narrowing
1. Hardware
  1. Hardware validation
    1. Functional verification
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Published In

EURO-DAC '94: Proceedings of the conference on European design automation

September 1994

697 pages

ISBN:0897916859

Chairman:
Jean Mermet
ECSI Office, Gie`res, France

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 23 September 1994

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EuroDAC94

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SIGDA

EuroDAC94: European Design Automation Conference

September 19 - 23, 1994

Grenoble, France

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Cited By

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Sakamoto TYamada TMukuno MMatsushita YHarada YYasuura HDe VIrwin MVerbauwhede IPiguet C(2002)Power analysis techniques for SoC with improved wiring modelsProceedings of the 2002 international symposium on Low power electronics and design10.1145/566408.566476(259-262)Online publication date: 12-Aug-2002
https://dl.acm.org/doi/10.1145/566408.566476
Kassab MCerny EAourid SKrodel TDewilde PRammig FMusgrave G(1998)Propagation of last-transition-time constraints in gate-level timing analysisProceedings of the conference on Design, automation and test in Europe10.5555/368058.368418(796-802)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368418
Zejda JCerny EShenoy SRumin N(1996)Bounding Switching Activity in CMOS Circuits Using Constraint ResolutionProceedings of the 1996 European conference on Design and Test10.5555/787259.787624Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787624

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Recommendations

High-Level Verification: Methods and Tools for Verification of System-Level Designs

Gate leakage reduction for scaled devices using transistor stacking

Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes