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EDAC 1994: Paris, France
- Robert Werner:
EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France. IEEE Computer Society 1994, ISBN 0-8186-5410-4
Session 1A: Processor Architecture
- George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos:
Design and Implementation of a High-Performance, Modular, Sorting Engine. 2-8 - Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel:
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. 9-13 - T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier:
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. 14-18
Session 1B: System Level Transformation and Micro Code Generation
- Frank H. M. Franssen, Lode Nachtergaele, Hans Samsom, Francky Catthoor, Hugo De Man:
Control flow optimization for fast system simulation and storage minimization. 20-24 - Shan-Hsi Huang, Jan M. Rabaey:
Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations. 25-30 - Clifford Liem, Trevor C. May, Pierre G. Paulin:
Instruction-Set Matching and Selection for DSP and ASIP Code Generation. 31-37
Session 1C: Testing Sequential Circuits.
- Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel:
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. 40-45 - Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda
:
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. 46-50 - Franco Fummi, Donatella Sciuto, Micaela Serra:
A Functional Approach to Delay Faults Test Generation for Sequential Circuits. 51-57
Session 2A: System Design and Mixed A/D Synthesis
- Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet:
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. 60-64 - Fermín Calvo, Pierre Plaza, Pedro Mateos:
ICM2 IC: a new ATM switching element for 2.48 Gb/s communications. 65-69 - Rob van Dongen, Vincent Rikkink:
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array. 70-74 - Dorine Gevaert, Jozef Vanneuville, Jiri Nedved, Jan Sevenhans:
Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End. 75-79
Session 2B: Circuit Optimization and Partitioning
- Hitesh Ajuha, Premachandran R. Menon:
Delay Reduction by Segment Substitution. 82-86 - Bernhard Rohfleisch, Franc Brglez:
Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. 87-93 - Lakshmikanth Ghatraju, Mostafa I. H. Abd-El-Barr, Carl McCrosky:
High-Level Synthesis of Digital Circuits by Finding Fixpoints. 94-98 - Daniel R. Brasen, Gabriele Saucier:
FPGA Partitioning for Critical Paths. 99-103
Session 2C: BIST Techniques
- Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer:
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. 106-112 - Albrecht P. Stroele:
Signature Analysis for Sequential Circuits with Reset. 113-118 - Ian G. Harris, Alex Orailoglu:
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. 119-123 - Richard Illman, D. J. Traynor:
A Fragmented Register Architecture and Test Advisor for BIST. 124-129
Session 3A: Finite State Machine Verification
- Ben Chen, Michihiro Yamazaki, Masahiro Fujita:
Bug Identification of a Real Chip Design by Symbolic Model Checking. 132-136 - Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
A State Space Decomposition Algorithm for Approximate FSM Traversal. 137-141 - Johannes Helbig, Peter Kelb:
An OBDD-Representation of Statecharts. 142-149
Session 3C: Fault Modeling
- Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc:
A Functionality Fault Model: Feasibility and Applications. 152-158 - Michele Favalli, Marcello Dalpasso
Modeling of Broken Connections Faults in CMOS ICs. 159-164 - Brian Chess, Tracy Larrabee:
Generating Test Patterns for Bridge Faults in CMOS ICs. 165-170 - Ralf Hahn
A Hierarchical Approach to Fault Collapsing. 171-176
Session 4A: Synchronous Finite State Machines
- Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin:
Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach. 178-183 - Yosinori Watanabe, Robert K. Brayton:
State Minimization of Pseudo Non-Deterministic FSM's. 184-191 - Maurizio Damiani:
Nondeterministic finite-state machines and sequential don't cares. 192-198
Session 4B: New BDD-Concepts
- Jochen Bern, Jordan Gergov, Christoph Meinel, Anna Slobodová:
Boolean Manipulation with Free BDD's. First Experimental Results. 200-207 - Michel Langevin, Eduard Cerny:
An Extended OBDD Representation for Extended FSMs. 208-213 - Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. 214-218
Session 4C: Applications of Boundary Scan
- Oliver F. Haberl, Thomas Kropf:
Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface. 220-225 - Chauchin Su:
Random Testing of Interconnects in A Boundary Scan Environment. 226-231 - Matti Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt:
Boundary Scan Testing Combined with Power Supply Current Monitoring. 232-235
Session 5A: DSP Implementations
- Roberto Sarmiento, Kamran Eshraghian:
Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology. 238-244 - Pierre Coulomb, François Pogodalla:
PLFP256 A Pipelined Fourier Processor. 245-249 - A. Vacher, M. Benkhebbab, Alain Guyot, T. Rousseau, Ali Skaf:
A VLSI Implementation of Parallel Fast Fourier Transform. 250-255 - D. Jacquet, Gabriele Saucier:
Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network. 256-260
Session 5B: Algorithmic Transformations in High-Level Synthesis
- Loganath Ramachandran, Daniel Gajski, Viraphol Chaiyakul:
An Algorithm for Array Variable Clustering. 262-266 - Mani B. Srivastava, Miodrag Potkonjak:
Transforming Linear Systems for Joint Latency and Throughout Optimization. 267-271 - Sandeep Bhatia, Niraj K. Jha:
Genesis: A Behavioral Synthesis System for Hierarchical Testability. 272-276 - Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin:
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. 277-281
Session 5C: DFT for Delay Faults and Sequential Machines
- Anton Vuksic, Karl Fuchs:
A New BIST Approach for Delay Fault Testing. 284-288 - Chih-Ang Chen, Sandeep K. Gupta:
BIST Test Pattern Generators for Stuck-Open and Delay Testing. 289-296 - Wuudiann Ke, Premachandran R. Menon:
Synthesis of Delay-Verifiable Two-Level Circuits. 297-301 - Sying-Jyan Wang:
Synthesis of Sequential Machines with Reduced Testing Cost. 302-306
Session 6A: Estimation During High-Level Synthesis
- Champaka Ramachandran, Fadi J. Kurdahi:
Incorporating the Controller Effects During Register Transfer Level Synthesis. 308-313 - Nancy D. Holmes, Daniel Gajski:
An Algorithm for Generation of Behavioral Shape Functions. 314-318 - Mehmet Emin Dalkiliç, Vijay Pitchumani:
Optimal Operation Scheduling Using Resource Lower Bound Estimations. 319-324 - Douglas M. Grant, Jef L. van Meerbergen, Paul E. R. Lippens:
Optimization of Address Generator Hardware. 325-329
Session 6B: Towards Statistical and High-Level Timing Analysis
- Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer:
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. 332-337 - Mukund Sivaraman, Andrzej J. Strojwas:
Towards Incorporating Device Parameter Variations in Timing Analysis. 338-342 - Jürgen Frößl, Thomas Kropf:
A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation. 343-348 - C. Safinia, Régis Leveugle, Gabriele Saucier:
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. 349-353
Session 6C: Bridging Faults in Testing
- Rosa Rodríguez-Montañés, Joan Figueras:
Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability. 356-360 - Manoj Sachdev:
Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. 361-365 - Eugeni Isern, Joan Figueras:
Test of Bridging Faults in Scan-based Sequential Circuits. 366-370 - Richard McGowen, F. Joel Ferguson:
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT. 371-375
Session 7A: Specification and Synthesis of System Interfaces
- Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin, Hugo De Man:
A Generalized Signal Transition Graph Model for Specification of Complex Interfaces. 378-384 - Franz Korf, Rainer Schlör:
Interface Controller Synthesis from Requirement Specifications. 385-394 - Sanjiv Narayan, Daniel Gajski:
Synthesis of System-Level Bus Interfaces. 395-399
Session 7C: Routing
- Henrik Esbensen, Pinaki Mazumder:
A Genetic Algorithm for the Steiner Problem in a Graph. 402-406 - Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess:
On Design Rule Correct Maze Routing. 407-411 - Yu-Liang Wu, Malgorzata Marek-Sadowska:
An Efficient Router for 2-D Field Programmable Gate Arrays. 412-416
Session 8A: Performance Issues in Physical Design
- J. Akita, K. Asada:
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability. 420-424 - How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang:
Cell Height Driven Transistor Sizing in a Cell Based Module Design. 425-429 - Bernard A. McCoy, Gabriel Robins:
Non-Tree Routing. 430-434
Session 8C: Various Views on Testing Efficiency
- José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams:
Fault Modeling and Defect Level Projections in Digital ICs. 436-442 - Hua Xue, Chennian Di, Jochen A. G. Jess:
Probability Analysis for CMOS Floating Gate Faults. 443-448 - Mohamed Jamoussi, Bozena Kaminska:
M-Testability: An Approach for Data-Path Testability Evaluation. 449-455
Session 9A: Design Methodologies for the System-Level
- Daniel Gajski, Frank Vahid, Sanjiv Narayan:
A System-Design Methodology: Executable-Specification Refinement. 458-463 - Tarek Ben Ismail, Kevin O'Brien, Ahmed Amine Jerraya:
Interactive System-level Partitioning with PARTIF. 464-468 - Martyn Edwards, John Forrest:
A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems. 469-473 - Jiro Naganuma, Takeshi Ogura, Tamio Hoshino:
High-Level Design Validation Using Algorithmic Debugging. 474-480
Session 9B: Applications of Scheduling in High-Level Synthesis
- Bruno Rouzeyre, D. Dupont, Georges Sagnes:
Component Selection, Scheduling and Control Schemes for High Level Synthesis. 482-489 - Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man:
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. 490-494 - Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani:
Scheduling with Environmental Constraints based on Automata Representations. 495-501 - Koen Schoofs, Gert Goossens, Hugo De Man:
Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures. 502-506
Session 9C: Delay Test
- Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee:
TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. 508-512 - Hannes C. Wittmann, Manfred Henftling:
Efficient Path Identification for Delay Testing - Time and Space Optimization. 513-517 - D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. 518-523 - Arno Kunzmann, Frank Böhland:
Gate-Delay Fault Test with Conventional Scan-Design. 524-528
Session 10A: Tools and Methods for Analogue System Design
- Stéphane Donnay, Koen Swings, Georges G. E. Gielen
A Methodology for Analog Design Automation in Mixed-Signal ASICs. 530-534 - Vincent Moser, Pascal Nussbaum, Hans Peter Amann, Luc Astier, Fausto Pellandini:
A Graphical Approach to Analogue Behavioural Modelling. 535-539 - Eamonn Byrne, Oliver McCarthy, David Lucas, Brian Donnellan:
An Overview of Analogue Optimisation Using "AD-OPT". 540-545 - Makoto Ikeda, Kunihiro Asada:
A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. 546-550
Session 10B: Logic, Circuit, and Yield Simulation Technologies
- Yih-Lang Li, Cheng-Wen Wu:
Logic and Fault Simulation by Cellular Automata. 552-556 - Kimon W. Michaels, Andrzej J. Strojwas:
Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. 557-561 - Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng:
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits. 562-566 - Zhihua Wang, Stephen W. Director:
An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance. 567-571
Session 10C: DFT for Datapaths, Controllers, and Arrays
- Michael Nicolaidis, Hakim Bederr:
Efficient Implementations of Self-Checking Multiply and Divide Arrays. 574-579 - Sybille Hellebrand, Hans-Joachim Wunderlich:
Synthesis of Self-Testable Controllers. 580-585 - Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu:
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. 586-590 - Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
Automatic Synthesis of BISTed Data Paths From High Level Specification. 591-598
Session 11A: Framework Services for Productivity Improvement
- M. Straube, Wolfgang Wilkes, Gunter Schlageter:
HANDICAP - A System for Design Consulting. 600-604 - Gunnar Bartels, Peter M. Kist, Kees Schot, Mattie N. Sim:
Flow Management Requirements of a Test Harness for Testing the Reliability of an Electronic CAD System. 605-609 - Sandip Parikh, Michael L. Bushnell, James Sienicki, Ganesh Ramakrishnan:
Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. 610-617
Session 11B: Techniques and Applications for BDDs
- Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska:
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. 620-624 - R. Iris Bahar
Timing Analysis of Combinational Circuits using ADD's. 625-629 - Bernd Wurth, Norbert Wehn:
Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization. 630-634
Session 11C: High-Level Verification
- Paolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas:
System-Level Modeling and Verification: a Comprehensive Design Methodology. 636-640 - Peter T. Breuer
Clean formal semantics for VHDL. 641-647 - Klaus Schneider, Thomas Kropf, Ramayya Kumar:
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. 648-652
Poster Session
- N. M. Vitsyn:
The Russian EDA Standards Activities. 654 - Thomas Johansson, L. R. Virtanen, J. M. Gobbi:
"Underground Capacitors" Very Efficient Decoupling for High Performance UHF Signal Processing ICs. 655 - Michel Robert, Patrick Gorria, Johel Mitéran, S. Turgis:
Design of a Real Time Geometric Classifier. 656 - Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto:
From Behavioral Description to Systolic Array Based Architectures. 657 - Abdessatar Abderrahman, Bozena Kaminska, Yvon Savaria:
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. 658 - H. H. Ahmad, R. J. Mack:
AREAL: Automated Reasoning Expert for Analogue Layout. 659 - Jean-Claude Dufourd, Jean-François Naviner:
An Optimizable Model for Process Independent Symbolic Design. 660 - Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin:
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. 661 - Wolfgang Vermeiren, Bernd Straube, Günter Elst:
A Suggestion for Accelerating the Analog Fault Simulation. 662 - K. C. Koudakou:
Software Implementation and Statistical Optimization of Some Electronic Component's Lifetime. 663 - Andrea Boni, Giovanni Chiorboli, G. Franco, S. Mazzoleni, M. Ostacoli:
Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters. 664 - Salman Ahmed, Peter Y. K. Cheung, Phil Collins:
A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. 665 - Ad J. van de Goor, Yervant Zorian, Ivo Schanstra:
Functional Tests for Ring-Address SRAM-type FIFOs. 666 - Bernd Becker, Rolf Drechsler:
Testability of Circuits Derived from Functional Decision Diagrams. 667 - Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. 668 - Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary:
Multilevel Logic Synthesis of Very High Complexity Circuits. 669 - Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan:
Signal Transition Graph Transformations for Initializability. 670 - Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen:
Synthesis of Application-Specific Multiprocessor Systems. 671 - Peter Zepter, Thorsten Grötker:
Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations. 672
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