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"Iterative and Fully Pipelined High Throughput Efficient Architectures of ..."

Vijay Kumar Sharma, Saurabh Kumar, Kamala Kanta Mahapatra (2016)

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DOI: 10.1142/S0218126616500493

access: closed

type: Journal Article

metadata version: 2020-10-22

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Vijay Kumar Sharma, Saurabh Kumar, Kamala Kanta Mahapatra:
Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC. J. Circuits Syst. Comput. 25(5): 1650049:1-1650049:29 (2016)

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