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Sidharth Rao
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2020 – today
- 2024
- [c7]W. Kim, Valerio Pica
, N. Jossart, Farrukh Yasin, Kurt Wostyn, S. Couet, Sidharth Rao:
A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays. IMW 2024: 1-4 - 2023
- [c6]Sicong Yuan, Mottaqiallah Taouil, Moritz Fieback
Device-Aware Test for Back-Hopping Defects in STT-MRAMs. DATE 2023: 1-6 - [c5]Sicong Yuan, Ziwei Zhang, Moritz Fieback
Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs. ITC 2023: 236-245 - 2021
- [c4]Sidharth Rao
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. IMW 2021: 1-4
2010 – 2019
- 2019
- [c3]Kevin Garello, Farrukh Yasin, Hubert Hody, S. Couet
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. VLSI Circuits 2019: 194- - 2018
- [c2]Barry J. O'Sullivan, Simon Van Beek, Philippe J. Roussel, Sidharth Rao
Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown. IRPS 2018: 5-1 - [c1]Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. VLSI Circuits 2018: 81-82 - [i1]Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. CoRR abs/1810.10356 (2018)
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