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Arnaud Furnémont
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2020 – today
- 2023
- [j2]Saeideh Alinezhad Chamazcoti
, Mohit Gupta, Hyungrock Oh, Timon Evenblij
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 733-746 (2023) - [c11]Mohit Kumar Gupta, Manu Perumkunnil, Dwaipayan Biswas
Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications. ISCAS 2023: 1-5 - 2022
- [c10]Mohit Gupta, Manu Perumkunnil, Andrea Fantini, Saeideh Alinezhad Chamazcoti, Woojin Kim, Marie Garcia Bardon, Gouri Sankar Kar, Arnaud Furnémont:
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications. ESSDERC 2022: 241-244 - [c9]Maarten Rosmeulen, Cesar J. Lockhart de la Rosa
Liquid Memory and the Future of Data Storage. IMW 2022: 1-4 - 2021
- [c8]Hyungrock Oh, Attilio Belmonte, Manu Perumkunnil, Jérôme Mitard, Nouredine Rassoul
Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications. ESSDERC 2021: 275-278
2010 – 2019
- 2019
- [c7]Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta:
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC 2019: 13 - [c6]Timon Evenblij, Christian Tenllado, Manu Perumkunnil, Francky Catthoor, Sushil Sakhare, Peter Debacker, Gouri Sankar Kar, Arnaud Furnémont, Nicolas Bueno, José Ignacio Gómez Pérez
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs. ICCD 2019: 255-263 - [c5]Anastasiia Kruv, Antonio Arreghini, Mario Gonzalez, Devin Verreck, Geert Van den Bosch, Ingrid De Wolf
Impact of Mechanical Stress on the Electrical Performance of 3D NAND. IRPS 2019: 1-5 - [c4]Arnaud Furnémont:
New Memory Technology, Design and Architecture Co-Optimization to Enable Future System Needs. VLSI-DAT 2019: 1 - [c3]Kevin Garello, Farrukh Yasin, Hubert Hody, S. Couet
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. VLSI Circuits 2019: 194- - 2018
- [c2]Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, José Ignacio Gómez
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. DATE 2018: 103-108 - [i1]Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. CoRR abs/1810.10356 (2018) - 2017
- [j1]Raf Appeltans
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1204-1214 (2017) - [c1]Manu Komalan, Sushil Sakhare, Trong Huynh Bao, Siddharth Rao
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. ISCAS 2017: 1-4
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