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Junning Chen
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Journal Articles
- 2023
- [j25]Qiang Zhao
, Hanwen Dong, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Junning Chen, Xiulong Wu:
Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments. Int. J. Circuit Theory Appl. 51(1): 398-409 (2023) - [j24]Zhiting Lin
In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations. IEEE J. Solid State Circuits 58(5): 1472-1486 (2023) - 2022
- [j23]Junning Chen:
Information sharing model of upstream supply chain based on embedded technology. Int. J. Inf. Commun. Technol. 21(4): 412-428 (2022) - [j22]Jin Zhang
In-Memory Multibit Multiplication Based on Bitline Shifting. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 354-358 (2022) - [j21]Pei Huang
Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2011-2015 (2022) - [j20]Yue Zhao
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 566-578 (2022) - 2021
- [j19]Zhiting Lin
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. IEEE J. Solid State Circuits 56(8): 2550-2562 (2021) - [j18]Zhiting Lin
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. IEEE J. Solid State Circuits 56(9): 2832-2844 (2021) - 2020
- [j17]Zhiting Lin
Challenges and Solutions of the TFET Circuit Design. IEEE Trans. Circuits Syst. 67-I(12): 4918-4931 (2020) - [j16]Zhiting Lin
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 607-619 (2020) - [j15]Qiang Zhao
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 848-852 (2020) - [j14]Zhiting Lin
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1316-1320 (2020) - 2019
- [j13]Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
An inverter chain with parallel output nodes for eliminating single-event transient pulse. IEICE Electron. Express 16(4): 20181118 (2019) - [j12]Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A single event upset tolerant latch with parallel nodes. IEICE Electron. Express 16(11): 20190208 (2019) - [j11]Chunyu Peng
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 407-415 (2019) - 2018
- [j10]Junning Chen, Hailun Jiang, Fangfei Li, Baichun Hu, Ying Wang, Mingxing Wang, Jian Wang, Mao-Sheng Cheng:
Computational insight into dengue virus NS2B-NS3 protease inhibition: A combined ligand- and structure-based approach. Comput. Biol. Chem. 77: 261-271 (2018) - [j9]Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng:
Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique. IEICE Electron. Express 15(10): 20180332 (2018) - [j8]Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination. IEICE Electron. Express 15(15): 20180604 (2018) - [j7]Chunyu Peng
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 584-588 (2018) - 2017
- [j6]Zhiting Lin
A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process. IEEE J. Solid State Circuits 52(3): 669-677 (2017) - 2016
- [j5]Zhengping Li, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, Junning Chen:
Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier. IEICE Electron. Express 13(7): 20150951 (2016) - 2015
- [j4]Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen:
A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier. IEICE Electron. Express 12(5): 20150102 (2015) - [j3]Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen:
Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]. IEICE Electron. Express 12(7): 20158001 (2015) - [j2]Shoubiao Tan, Wenjuan Lu, Chunyu Peng, Zhengping Li, Youwu Tao, Junning Chen:
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier. Frontiers Inf. Technol. Electron. Eng. 16(8): 700-706 (2015) - 2013
- [j1]Xiulong Wu, Minghua Li, Zhiting Lin, Mengyuan Xi, Junning Chen:
The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip. Sensors 13(7): 8771-8785 (2013)
Conference and Workshop Papers
- 2006
- [c2]Shan Gao, Junning Chen, Daoming Ke, Xiulong Wu:
A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design. APCCAS 2006: 1465-1468 - [c1]Yuehua Dai, Yuan Hu, Qi Liu, Daoming Ke, Junning Chen:
Physics-based Modeling and Simulation of Dual Material Gate(DMG) LDMOS. APCCAS 2006: 1500-1503
Coauthor Index
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