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Fu-Lung Hsueh
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2010 – 2019
- 2018
- [j4]Shang-Fu Yeh, Kuo-Yu Chou, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh:
A 0.66erms- Temporal-Readout-Noise 3-D-Stacked CMOS Image Sensor With Conditional Correlated Multiple Sampling Technique. IEEE J. Solid State Circuits 53(2): 527-537 (2018) - 2017
- [j3]Feng-Wei Kuo, Sandro Binsfeld Ferreira, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Iman Madadi, Massoud Tohidian, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski:
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. IEEE J. Solid State Circuits 52(4): 1144-1162 (2017) - 2016
- [j2]Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski:
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. IEEE J. Solid State Circuits 51(7): 1547-1565 (2016) - [c22]Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. ISSCC 2016: 36-37 - [c21]Charles Chih-Min Liu, Manoj M. Mhala, Chin-Hao Chang, Honyih Tu, Po-Sheng Chou, Calvin Chao, Fu-Lung Hsueh:
6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias. ISSCC 2016: 124-125 - [c20]Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. ISSCC 2016: 184-185 - [c19]Makoto Ikeda, David Stoppa, Michiel A. P. Pertijs, Yusuke Oike, Maurits Ortmanns, Vadim Ivanov, Fu-Lung Hsueh:
F5: Advanced IC design for ultra-low-noise sensing. ISSCC 2016: 506-509 - [c18]Feng-Wei Kuo, Sandro Binsfeld Ferreira, Masoud Babaie, Huan-Neng Ron Chen, Lan-chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski:
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. VLSI Circuits 2016: 1-2 - 2015
- [c17]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski:
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. ESSCIRC 2015: 356-359 - [c16]Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang:
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. ISSCC 2015: 1-3 - [c15]Shang-Fu Yeh, Kuo-Yu Chou, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh:
A 0.66e-rms temporal-readout-noise 3D-stacked CMOS image sensor with conditional correlated multiple sampling (CCMS) technique. VLSIC 2015: 84- - 2014
- [c14]Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh:
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS. ISSCC 2014: 144-145 - [c13]Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski:
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. VLSIC 2014: 1-2 - [c12]Charles Chih-Min Liu, Chin-Hao Chang, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh, Szu-Ying Chen, Vincent Hsu, Jen-Cheng Liu, Dun-Nien Yaung, Shou-Gwo Wuu:
A peripheral switchable 3D stacked CMOS image sensor. VLSIC 2014: 1-2 - 2013
- [c11]Fu-Lung Hsueh, Shinichiro Mutoh:
Session 11 overview: Emerging memory and wireless technology. ISSCC 2013: 190-191 - [c10]I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh:
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. ISSCC 2013: 414-415 - 2012
- [j1]Wen-Shen Chou, Tzu-Chi Huang, Yu-Huei Lee, Yao-Yi Yang, Yi-Ping Su, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Kuei-Ann Wen, Ying-Chih Hsu, Yung-Chow Peng, Fu-Lung Hsueh:
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter. IEEE J. Solid State Circuits 47(7): 1568-1584 (2012) - [c9]Tao-Wen Chung, Tsung-Ching Huang, S. Chung, Ming-Chieh Huang, Chih-Chang Lin, Chan-Hong Chern, Fu-Lung Hsueh:
A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS. CICC 2012: 1-4 - [c8]Alison J. Burdett, Fu-Lung Hsueh:
Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommittee. ISSCC 2012: 290-291 - 2011
- [c7]Yi-Kai Lo, Wentai Liu, Kuanfu Chen, Ming-Hsien Tsai, Fu-Lung Hsueh:
A 64-channel neuron recording system. EMBC 2011: 2862-2865 - [c6]Kuanfu Chen, Ming-Hsien Tsai, Fu-Lung Hsueh, Wentai Liu:
Analysis and design of data transmission protocol for 1024-channel retinal prosthesis. EMBC 2011: 4010-4013 - [c5]Tzu-Chi Huang, Wen-Shen Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Yung-Chow Peng, Fu-Lung Hsueh:
55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter. ESSCIRC 2011: 383-386 - 2010
- [c4]W. M. Young, Chua-Huang Huang, Alan P. Su, Chewnpu Jou, Fu-Lung Hsueh:
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example. ASP-DAC 2010: 821-824 - [c3]Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu:
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. CICC 2010: 1-4 - [c2]Hsieh-Hung Hsieh, Fu-Lung Hsueh, Chewnpu Jou, Fred Kuo, Sean Chen, Tzu-Jin Yeh, Kevin Kai-Wen Tan, Po-Yi Wu, Yu-Ling Lin, Ming-Hsien Tsai:
A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS. CICC 2010: 1-4
2000 – 2009
- 2007
- [c1]Wen-Shen Chou, Shu-Chieh Yang, Fu-Lung Hsueh, Heng-Chang Huang, Chih-Ji Hsiao:
A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process. ISCAS 2007: 3594-3597
Coauthor Index
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