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research-article

A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example

Authors:

Chua-Huang Huang,

Fu-Lung HsuehAuthors Info & Claims

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Pages 821 - 824

Published: 18 January 2010 Publication History

Abstract

This paper presents the first published industrial practice (to the best of our knowledge) to reuse high-level/C++ system simulation model through OSCI TLM 2.0 Library to verify its corresponding RTL implementation in FPGA. ESL verification methodology is employed in the design regression of EPC C1Gen2 RFID tag. Around 200 times speedup is observed using ESL over conventional RTL simulation in regression runs (after logic bug fixes). This clearly shows ESL verification is a successful candidate to reuse high-level test harness for IC functional verification, especially in today's increasingly complex IC design world. On top of the successful use of the ESL functional verification flow on the design, we also show the infrastructure to use SystemC Verification Library (SCV) for formal verification. The functional and formal verification combined is thus the proposed ESL verification methodology.

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Cited By

Ni NPeng YHutchings BBetz V(2013)Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435346(278-278)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435346

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Information & Contributors

Information

Published In

cover image ACM Conferences

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

January 2010

920 pages

ISBN:9781605588377

General Chair:
Youn-Long Lin
National Tsing Hua University

Sponsors

TICD: TICD
SIGDA: ACM Special Interest Group on Design Automation
IEEE CAS

Publisher

IEEE Press

Publication History

Published: 18 January 2010

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Research-article

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ASPDAC '10

Sponsor:

TICD
SIGDA

ASPDAC '10: Asia and South Pacific Design Automation Conference

January 18 - 21, 2010

Taipei, Taiwan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

Ni NPeng YHutchings BBetz V(2013)Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435346(278-278)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435346

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