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Ki-Tae Park
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2010 – 2019
- 2018
- [j11]Chulbum Kim
, Doo-Hyun Kim, Woopyo Jeong, Hyun-Jin Kim, Il-Han Park, Hyun Wook Park, Jong-Hoon Lee, Jiyoon Park, Yang-Lo Ahn, Ji Young Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Nahyun Kim, Hwajun Jang, Jonghoon Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sanggi Hong, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, Dae-Seok Byeon, Jin-Yub Lee, Ki-Tae Park, Kyehyun Kyung:
A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory. IEEE J. Solid State Circuits 53(1): 124-133 (2018) - [j10]Wongi S. Na, Dong-Woo Seo, Byeong-Cheol Kim, Ki-Tae Park:
Effects of Applying Different Resonance Amplitude on the Performance of the Impedance-Based Health Monitoring Technique Subjected to Damage. Sensors 18(7): 2267 (2018) - [c16]Ki-Tae Park, Yan Li, Leland Chang:
Session 20 overview: Flash-memory solutions: Memory subcommittee. ISSCC 2018: 334-335 - [c15]Wooseong Cheong, Chanho Yoon, Seonghoon Woo, Kyuwook Han, Daehyun Kim, Chulseung Lee, Youra Choi, Shine Kim, Dongku Kang, Geunyeong Yu, Jaehong Kim, Jaechun Park, Ki-Whan Song, Ki-Tae Park, Sangyeun Cho, Hwaseok Oh, Daniel D. G. Lee, Jin-Hyeok Choi, Jaeheon Jeong:
A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time. ISSCC 2018: 338-340 - [c14]Seungjae Lee
A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput. ISSCC 2018: 340-342 - [c13]Jaeha Kim, Ki-Tae Park:
EE6: Can artificial intelligence replace my job? The dawn of a new IC industry with AI. ISSCC 2018: 531-533 - 2017
- [j9]Dongku Kang, Woopyo Jeong, Chulbum Kim, Doo-Hyun Kim, Yong-Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Cheon An Lee, Young-Sun Min, Moosung Kim, Ansoo Park, Jae-Ick Son, In-Mo Kim, Pansuk Kwak, Bong-Kil Jung, Doosub Lee, Hyunggon Kim, Jeong-Don Ihm, Dae-Seok Byeon, Jin-Yup Lee, Ki-Tae Park, Kyehyun Kyung:
256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers. IEEE J. Solid State Circuits 52(1): 210-217 (2017) - [c12]Takashi Kono, Ki-Tae Park, Leland Chang:
Session 11 overview: Nonvolatile memory solutions. ISSCC 2017: 194-195 - [c11]Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, Il-Han Park, Hyun Wook Park, Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jong-Hoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoon Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, Byunghoon Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sunghoon Kim, Dongkyu Yoon, Ki-Sung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, Dae-Seok Byeon, Jin-Yub Lee, Ki-Tae Park, Kyehyun Kyung:
11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. ISSCC 2017: 202-203 - 2016
- [j8]Woopyo Jeong, Jae-Woo Im, Doo-Hyun Kim, Sangwan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, Hyun Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jinho Ryu, Sang-Won Shim, Kyung-Tae Kang, Jeong-Don Ihm, In-Mo Kim, Doosub Lee, Ji-Ho Cho, Moosung Kim, Jae-hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. IEEE J. Solid State Circuits 51(1): 204-212 (2016) - [c10]Dongku Kang, Woopyo Jeong, Chulbum Kim, Doo-Hyun Kim, Yong-Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doo-Gon Kim, Young-Sun Min, Moosung Kim, Ansoo Park, Jae-Ick Son, In-Mo Kim, Pansuk Kwak, Bong-Kil Jung, Doosub Lee, Hyunggon Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. ISSCC 2016: 130-131 - [c9]Seungjae Lee
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. ISSCC 2016: 138-139 - 2015
- [j7]Hae-Bum Yun, Ganesh Sundaresan, Youngwoo Jung, Jong-Woo Kim, Ki-Tae Park:
Novel Pattern Detection Algorithm for Monitoring Phase Change of Moisture on Concrete Pavement Using Surface Temperature Data. J. Comput. Civ. Eng. 29(2) (2015) - [j6]Ki-Tae Park, Sangwan Nam, Dae-Han Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Minsu Kim, Hyun Wook Park, Sang-Won Shim, Kyung-Min Kang, Sang-Won Park, Kangbin Lee, Hyun-Jun Yoon, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dae-Seok Byeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Jeong-Hyuk Choi, Kinam Kim:
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. IEEE J. Solid State Circuits 50(1): 204-213 (2015) - [c8]Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, Sangwan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, Hyun Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jinho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, Ohsuk Kwon, Ji-Sang Lee, Moosung Kim, Sang-Hyun Joo, Jae-hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. ISSCC 2015: 1-3 - [c7]Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip. ISSCC 2015: 1-3 - 2014
- [c6]Ki-Tae Park, Jin-Man Han, Dae-Han Kim, Sangwan Nam, Kihwan Choi, Minsu Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Kyung-Min Kang, Myung-Hoon Choi, Dong-Hun Kwak, Hyun Wook Park, Sang-Won Shim, Hyun-Jun Yoon, Doo-Hyun Kim, Sang-Won Park, Kangbin Lee, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jeunghwan Park, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dongkyu Youn, Won-Tae Kim, Taehyun Kim, Sung-Jun Kim, Sungwhan Seo, Hyunggon Kim, Dae-Seok Byeon, Hyang-Ja Yang, Moosung Kim, Myong-Seok Kim, Jinseon Yeon, Jae-hoon Jang, Han-Soo Kim, Woonkyung Lee, Duheon Song, Sungsoo Lee, Kyehyun Kyung, Jeong-Hyuk Choi:
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming. ISSCC 2014: 334-335 - 2012
- [c5]Seung-Hwan Shin, Dong-Kyo Shim, Jaeyong Jeong, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi, Tae-Young Kim, Hyun Wook Park, Hyun-Jun Yoon, Youngsun Song, Yoon-Hee Choi, Sang-Won Shim, Yang-Lo Ahn, Ki-Tae Park, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun:
A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory. VLSIC 2012: 132-133 - 2011
- [c4]Ki-Tae Park, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi, In-Mo Kim, Bo-Geun Kim, Min-Seok Kim, Yoon-Hee Choi, Seung-Hwan Shin, Youngson Song, Joo-Yong Park, Jae-Eun Lee, Chang-Gyu Eun, Ho-Chul Lee, Hyeong-Jun Kim, Jun-Hee Lee, Jong-Young Kim, Tae-Min Kweon, Hyun-Jun Yoon, Taehyun Kim, Dong-Kyo Shim, Jongsun Sel, Ji-Yeon Shin, Pansuk Kwak, Jin-Man Han, Keon-Soo Kim, Sungsoo Lee, Youngho Lim, Tae-Sung Jung:
A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology. ISSCC 2011: 212-213 - 2010
- [j5]Myounggon Kang, Ki-Tae Park, Youngsun Song, Sungsoo Lee, Yunheub Song, Youngho Lim:
A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory. IEICE Trans. Electron. 93-C(2): 182-186 (2010) - [j4]Youngsun Song, Ki-Tae Park, Myounggon Kang, Yunheub Song, Sungsoo Lee, Youngho Lim, Kang-Deog Suh:
Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory. IEICE Trans. Electron. 93-C(3): 423-425 (2010) - [j3]Ki-Tae Park, Youngsun Song, Myounggon Kang, Sungsoo Lee, Youngho Lim, Kang-Deog Suh, Chilhee Chung:
Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories. IEEE J. Solid State Circuits 45(10): 2165-2172 (2010) - [c3]Hyunggon Kim, Jung-Hoon Park, Ki-Tae Park, Pansuk Kwak, Ohsuk Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyun Cho, Juseok Lee, Jungho Song, Soowoong Lee, Hyukjun Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, Kyehyun Kyung, Yong-Ho Lim, Chilhee Chung:
A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface. ISSCC 2010: 442-443
2000 – 2009
- 2009
- [j2]Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doo-Gon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Yeong-Taek Lee, Soon-Moon Jung, Changhyun Kim:
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. IEEE J. Solid State Circuits 44(1): 208-216 (2009) - 2008
- [j1]Ki-Tae Park, Myounggon Kang, Doogon Kim, Soonwook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, Kinam Kim:
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories. IEEE J. Solid State Circuits 43(4): 919-928 (2008) - [c2]Ki-Tae Park, Doo-Gon Kim, Soonwook Hwang, Myounggon Kang, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim, Won-Seong Lee:
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. ISSCC 2008: 510-511 - 2003
- [c1]Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong:
An MTCMOS design methodology and its application to mobile computing. ISLPED 2003: 110-115
Coauthor Index
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