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Seon-Kyoo Lee
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2020 – today
- 2024
- [c12]Jaeho Lee, Kyongsu Lee, Jae-Yoon Sim, Seon-Kyoo Lee:
A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect. VLSI Technology and Circuits 2024: 1-2 - [c11]Dongjun Park, Heesung Roh, Seon-Kyoo Lee, Jae-Yoon Sim:
A $94\text{fs}_{\text{rms}}$-Jitter and -249.3dB FoM 4.0GHz Ring-Oscillator-Based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch. VLSI Technology and Circuits 2024: 1-2 - 2021
- [j10]Dae-Hoon Na
, Jang-Woo Lee, Seon-Kyoo Lee
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. IEEE J. Solid State Circuits 56(4): 1129-1140 (2021) - [c10]Chiweon Yoon, Hyunggon Kim, Seon-Kyoo Lee
Issues and Key Technologies for Next Generation 3D NAND. ICEIC 2021: 1-4 - 2020
- [c9]Jang-Woo Lee, Dae-Hoon Na
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. VLSI Circuits 2020: 1-2
2010 – 2019
- 2016
- [c8]Seungjae Lee
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. ISSCC 2016: 138-139 - 2015
- [c7]Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip. ISSCC 2015: 1-3 - 2014
- [j9]Seung-Hun Lee, Seon-Kyoo Lee
Current-Mode Transceiver for Silicon Interposer Channel. IEEE J. Solid State Circuits 49(9): 2044-2053 (2014) - [j8]Hyunsoo Ha
A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 840-844 (2014) - 2013
- [j7]Seon-Kyoo Lee
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation. IEEE J. Solid State Circuits 48(9): 2118-2127 (2013) - [j6]Seon-Kyoo Lee
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface. IEEE Trans. Circuits Syst. II Express Briefs 60-II(2): 91-95 (2013) - [c6]Seon-Kyoo Lee
A 95fJ/b current-mode transceiver for 10mm on-chip interconnect. ISSCC 2013: 262-263 - 2012
- [c5]Hyunsoo Ha
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling. CICC 2012: 1-4 - [c4]Young-Sik Kim, Seon-Kyoo Lee
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. ISSCC 2012: 136-138 - [c3]Seon-Kyoo Lee
A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation. ISSCC 2012: 140-142 - 2011
- [j5]Seon-Kyoo Lee
A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition. J. Electr. Comput. Eng. 2011: 701730:1-701730:7 (2011) - [j4]Young-Sang Kim, Seon-Kyoo Lee
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. IEEE J. Solid State Circuits 46(2): 435-444 (2011) - [j3]Seon-Kyoo Lee
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface. IEEE J. Solid State Circuits 46(3): 651-659 (2011) - [j2]Young Hun Seo, Seon-Kyoo Lee
A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 58-II(2): 70-74 (2011) - 2010
- [j1]Seon-Kyoo Lee
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS. IEEE J. Solid State Circuits 45(12): 2874-2881 (2010) - [c2]Seon-Kyoo Lee
A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS. ISSCC 2010: 482-483
2000 – 2009
- 2009
- [c1]Seon-Kyoo Lee
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate. ISSCC 2009: 184-185
Coauthor Index
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