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Chirag Sudarshan
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2020 – today
- 2024
- [j6]Mohammad Hassani Sadi
, Chirag Sudarshan, Norbert Wehn:
Novel adaptive quantization methodology for 8-bit floating-point DNN training. Des. Autom. Embed. Syst. 28(2): 91-110 (2024) - [i3]Nathan Leroux, Paul-Philipp Manea, Chirag Sudarshan, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci:
Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Models. CoRR abs/2409.19315 (2024) - 2023
- [c19]Gia Bao Thieu
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE 2023: 1-6 - [c18]Paul-Philipp Manea
Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories. NANOARCH 2023: 17:1-17:6 - 2022
- [j5]Chirag Sudarshan
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 367-380 (2022) - [c17]Chirag Sudarshan, Mohammad Hassani Sadi
Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training. ISCAS 2022: 1472-1476 - [c16]Lukas Steiner
A Framework for Formal Verification of DRAM Controllers. MEMSYS 2022: 6:1-6:7 - [c15]Chirag Sudarshan, Mohammad Hassani Sadi
A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions. SAMOS 2022: 362-379 - [c14]Chirag Sudarshan, Taha Soliman, Thomas Kämpfe
FeFET versus DRAM based PIM Architectures: A Comparative Study. VLSI-SoC 2022: 1-6 - [i2]Lukas Steiner, Chirag Sudarshan, Matthias Jung, Dominik Stoffel, Norbert Wehn:
A Framework for Formal Verification of DRAM Controllers. CoRR abs/2209.14021 (2022) - 2021
- [j4]Chirag Sudarshan
A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1615-1619 (2021) - [j3]Vladimir Rybalkin
Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. 93(12): 1467 (2021) - [c13]Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro
A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. ASP-DAC 2021: 35-42 - 2020
- [j2]Vladimir Rybalkin
Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. 92(11): 1219-1245 (2020) - [j1]Dimitrios Stathis
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. J. Signal Process. Syst. 92(11): 1323-1343 (2020) - [c12]Sven Müelich, Chirag Sudarshan, Christian Weis, Martin Bossert, Robert F. H. Fischer, Norbert Wehn:
Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory. MEMSYS 2020: 126-136 - [c11]Muhammad Mohsin Ghaffar, Chirag Sudarshan, Christian Weis, Matthias Jung, Norbert Wehn:
A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions. MEMSYS 2020: 158-168 - [c10]Marco V. Natale, Matthias Jung, Kira Kraft, Frederik Lauer
Efficient Generation of Application Specific Memory Controllers. MEMSYS 2020: 233-247
2010 – 2019
- 2019
- [c9]Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn
An In-DRAM Neural Network Processing Engine. ISCAS 2019: 1-5 - [c8]Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn
Fast validation of DRAM protocols with timed petri nets. MEMSYS 2019: 133-147 - [c7]Sven Müelich, Sebastian Bitzer, Chirag Sudarshan, Christian Weis, Norbert Wehn
Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements. REDUNDANCY 2019: 149-154 - [c6]Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. SAMOS 2019: 429-441 - [i1]Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn:
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR abs/1911.00889 (2019) - 2018
- [c5]Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. DATE 2018: 293-296 - [c4]Kira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn
Improving the error behavior of DRAM by exploiting its Z-channel property. DATE 2018: 1492-1495 - [c3]Christian Weis, Matthias Jung, Éder F. Zulian, Chirag Sudarshan, Deepak M. Mathew, Norbert Wehn
The Role of Memories in Transprecision Computing. ISCAS 2018: 1-5 - [c2]Kira Kraft, Deepak M. Mathew, Chirag Sudarshan, Matthias Jung, Christian Weis, Norbert Wehn
Efficient coding scheme for DDR4 memory subsystems. MEMSYS 2018: 148-157 - [c1]Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, Norbert Wehn
Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. MEMSYS 2018: 377-386
Coauthor Index
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