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Junghyuk Yoon
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2020 – today
- 2024
- [c3]Myoungsub Kim, Yooncheol Bae, Jaehyuk Park, Jeongho Yeon, Hyungjoon Shim, Sehyun Jin, Hyunsoo Kim, Sangchul Oh, Gapsok Do, Dongyeol Yun, Hyung Dong Lee, David Ahn, Junghun Lee, Muhui Park, Junghyuk Yoon, Jeongho Yi, Taekseung Kim, Gain Park, Seoungju Chung, Junho Cheon, Sujin Chae, Namkyun Park, Kyunghoon Kim, Dongyean Oh, Jaeyun Yi, Seonyong Cha:
First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory. VLSI Technology and Circuits 2024: 1-2
2010 – 2019
- 2019
- [j1]Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo
, Mi-Young Kim, Min-Chul Shin, Seokjoon Kang, Junghyuk Yoon, Taek-Seung Kim, Seung-Tak Ryu
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. IEEE J. Solid State Circuits 54(6): 1812-1823 (2019) - 2018
- [c2]Sung-Won Choi, Yeunhee Huh, Sang-Hui Park, Kye-Seok Yoon, Jun-Suk Bang, Se-Un Shin, Yong-Min Ju, Yu-Jin Yang, Junghyuk Yoon, Changyong Ahn, Taekseung Kim, Sung-Wan Hong, Gyu-Hyeong Cho:
A Quasi-Digital Ultra-Fast Capacitor-Less Low-Dropout Regulator Based on Comparator Control for x8 Current Spike of PCRAM Systems. VLSI Circuits 2018: 107-108 - 2014
- [c1]Aravinthan Athmanathan, Milos Stanisavljevic, Junho Cheon, Seokjoon Kang, Changyong Ahn, Junghyuk Yoon, Min-Chul Shin, Taekseung Kim, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou:
A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory. A-SSCC 2014: 137-140
Coauthor Index
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last updated on 2024-10-18 19:32 CEST by the dblp team
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