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Vito Boccuzzi
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2020 – today
- 2022
- [c7]Kadaba R. Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Vito Boccuzzi, Pavan Kumar Hanumolu:
High-Performance CMOS TIA for Data Center Optical Interconnects. BCICTS 2022: 9-16
2010 – 2019
- 2019
- [j11]Kadaba Lakshmikumar
, Alexander Kurylak
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links. IEEE J. Solid State Circuits 54(11): 3180-3190 (2019)
2000 – 2009
- 2006
- [j10]Jesús Arias Álvarez, Peter Kiss, Vladimir I. Prodanov, Vito Boccuzzi, Mihai Banu, David Bisbal, Jacinto San Pablo, Luis Quintanilla, Juan Barbolla:
A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers. IEEE J. Solid State Circuits 41(2): 339-351 (2006) - 2005
- [j9]Sander L. J. Gierkink, Dandan Li, Robert C. Frye, Vito Boccuzzi:
A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver. IEEE J. Solid State Circuits 40(9): 1909-1921 (2005) - [j8]Jesús Arias Álvarez, Peter Kiss, Vito Boccuzzi, Luis Quintanilla, Lourdes Enríquez
Nonlinearity correction for multibit ΔΣ DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1033-1041 (2005) - 2004
- [j7]Yorgos Palaskas, Yannis P. Tsividis, Vladimir I. Prodanov, Vito Boccuzzi:
A "divide and conquer" technique for implementing wide dynamic range continuous-time filters. IEEE J. Solid State Circuits 39(2): 297-307 (2004) - [j6]Arnoud P. van der Wel, Sander L. J. Gierkink, Robert C. Frye, Vito Boccuzzi, Bram Nauta
A robust 43-GHz VCO in CMOS for OC-768 SONET applications. IEEE J. Solid State Circuits 39(7): 1159-1163 (2004) - [j5]Jesús Arias Álvarez, Vito Boccuzzi, Luis Quintanilla, Lourdes Enríquez
Low-power pipeline ADC for wireless LANs. IEEE J. Solid State Circuits 39(8): 1338-1340 (2004) - [j4]Peter Kiss, Jesús Arias Álvarez, Dandan Li, Vito Boccuzzi:
Stable high-order delta-sigma digital-to-analog converters. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 200-205 (2004) - [c6]Sander L. J. Gierkink, Dandan Li, Robert C. Frye, Vito Boccuzzi:
A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver. CICC 2004: 629-632 - 2003
- [j3]Salvatore Levantino
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing. IEEE J. Solid State Circuits 38(6): 895-904 (2003) - [j2]Sander L. J. Gierkink, Salvatore Levantino
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling. IEEE J. Solid State Circuits 38(7): 1148-1154 (2003) - [c5]Yorgos Palaskas, Yannis P. Tsividis, Vito Boccuzzi:
A power efficient channel selection filter/coarse AGC with no range switching transients. CICC 2003: 21-24 - [c4]Sander L. J. Gierkink, Robert C. Frye, Vito Boccuzzi:
Differentially "bathtub"-tuned CMOS VCO using inductively coupled varactors. ESSCIRC 2003: 501-504 - 2002
- [j1]Salvatore Levantino
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. IEEE J. Solid State Circuits 37(8): 1003-1011 (2002) - 2001
- [c3]Carlo Samori, Salvatore Levantino, Vito Boccuzzi:
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications. CICC 2001: 201-204 - [c2]Vladimir I. Prodanov, Vito Boccuzzi:
7V tristate-capable output buffer implemented in standard 2.5 V CMOS process. CICC 2001: 497-500
1990 – 1999
- 1998
- [c1]Vito Boccuzzi, Jack P. F. Glas:
Testing the double low-IF receiver architecture. PIMRC 1998: 370-374
Coauthor Index
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