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2020 – today
- 2024
- [j57]Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars. IEEE J. Solid State Circuits 59(12): 3915-3927 (2024) - [j56]Gabriele Zanoletti
, Lorenzo Scaletti
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1551-1555 (2024) - [c59]Simone Mattia Dartizio, Michele Rossoni
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. CICC 2024: 1-2 - [c58]Michele Rossoni
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM. ISSCC 2024: 188-190 - [c57]Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion. ISSCC 2024: 198-200 - [c56]Alessia Ceroni, Gabriele Zanoletti, Andrea Bonfanti, Carlo Samori:
A Highly Energy-Efficient FIA-based AZ-free Ring Amplifier for Pipeline-SAR ADCs. PRIME 2024: 1-4 - [c55]Riccardo Moleri, Simone Mattia Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j55]Francesco Buccoleri
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58(3): 634-646 (2023) - [j54]Francesco Tesolin
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. IEEE J. Solid State Circuits 58(9): 2466-2477 (2023) - [j53]Simone Mattia Dartizio
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. IEEE J. Solid State Circuits 58(12): 3320-3337 (2023) - [c54]Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ISSCC 2023: 78-79 - [c53]Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. ISSCC 2023: 82-83 - [c52]Luca Ricci, Lorenzo Scaletti
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j52]Mario Mercandelli
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits 57(2): 505-517 (2022) - [j51]Simone Mattia Dartizio
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57(6): 1723-1735 (2022) - [j50]Simone Mattia Dartizio
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57(12): 3538-3551 (2022) - [j49]Luca Bertulessi
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1858-1870 (2022) - [j48]Gabriele Bè
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3645-3649 (2022) - [c51]Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC 2022: 1-2 - [c50]Luca Ricci, Lorenzo Scaletti
Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs. ISCAS 2022: 900-904 - [c49]Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC 2022: 1-3 - [c48]Lorenzo Scaletti
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. NEWCAS 2022: 20-24 - 2021
- [j47]Saleh Karman
A Novel Topology of Coupled Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 989-997 (2021) - [j46]Luca Avallone
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2775-2786 (2021) - [c47]Mario Mercandelli, Luca Bertulessi
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. A-SSCC 2021: 1-3 - [c46]Carlo Samori, Luca Bertulessi
Digital PLLs: the modern timing reference for radar and communication systems. ESSCIRC 2021: 21-27 - [c45]Angelo Parisi
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity. ICECS 2021: 1-4 - [c44]Mario Mercandelli
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC 2021: 445-447 - [c43]Alessio Santiccioli, Mario Mercandelli
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC 2021: 456-458 - 2020
- [j45]Alessio Santiccioli
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits 55(12): 3349-3361 (2020) - [j44]Luca Avallone
Jitter Minimization in Digital PLLs with Mid-Rise TDCs. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 743-752 (2020) - [c42]Alessio Santiccioli, Mario Mercandelli
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. ISSCC 2020: 268-270 - [c41]Mario Mercandelli
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. ISSCC 2020: 274-276
2010 – 2019
- 2019
- [j43]Alessio Santiccioli
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE J. Solid State Circuits 54(11): 3149-3160 (2019) - [j42]Luca Bertulessi
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. IEEE J. Solid State Circuits 54(12): 3493-3502 (2019) - [j41]Alessio Santiccioli
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3775-3785 (2019) - [c40]Dmytro Cherniak, Carlo Samori
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper). CICC 2019: 1-8 - [c39]Alessio Santiccioli, Mario Mercandelli
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. CICC 2019: 1-4 - [c38]Luigi Grimaldi, Luca Bertulessi
A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. ISSCC 2019: 268-270 - 2018
- [j40]Mario Mercandelli
A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE J. Solid State Circuits 53(11): 3243-3255 (2018) - [j39]Dmytro Cherniak
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. IEEE J. Solid State Circuits 53(12): 3565-3575 (2018) - [j38]Dmytro Cherniak
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 914-924 (2018) - [c37]Dmytro Cherniak, Luigi Grimaldi, Carlo Samori
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators. ISCAS 2018: 1-5 - [c36]Alessandro Truppi, Carlo Samori
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. ISCAS 2018: 1-4 - [c35]Tuan Minh Vo
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs. ISCAS 2018: 1-4 - [c34]Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. ISSCC 2018: 248-250 - [c33]Luca Bertulessi
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. ISSCC 2018: 252-254 - 2017
- [c32]Dmytro Chemiak, Salvatore Levantino
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars. ISCAS 2017: 1-4 - [c31]Tuan Minh Vo
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL. ISCAS 2017: 1-4 - 2015
- [j37]Salvatore Levantino
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop. IEEE J. Solid State Circuits 50(11): 2678-2691 (2015) - [c30]Tsung-Hsien Lin
EP2: Lost art? Analog tricks and techniques from the masters. ISSCC 2015: 1 - 2014
- [j36]Salvatore Levantino
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs. IEEE J. Solid State Circuits 49(8): 1762-1772 (2014) - [j35]Makoto Nagata
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 49(12): 2743-2747 (2014) - [j34]Giovanni Marucci, Salvatore Levantino
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 26-36 (2014) - [c29]Giovanni Marzin, Salvatore Levantino
2.9 A Background calibration technique to control bandwidth in digital PLLs. ISSCC 2014: 54-55 - [c28]Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin, Salvatore Levantino
21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC. ISSCC 2014: 360-361 - 2013
- [j33]Federico Pepe
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band. IEEE J. Solid State Circuits 48(10): 2375-2389 (2013) - [j32]Salvatore Levantino
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. IEEE J. Solid State Circuits 48(10): 2419-2429 (2013) - [j31]Giovanni Marucci, Salvatore Levantino
Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 632-636 (2013) - [c27]Salvatore Levantino
Nonlinearity cancellation in digital PLLs (Invited paper). CICC 2013: 1-8 - [c26]Giovanni Marzin, Andrea Fenaroli, Giovanni Marucci, Salvatore Levantino
A spur cancellation technique for MDLL-based frequency synthesizers. ISCAS 2013: 165-168 - [c25]Giovanni Marucci, Salvatore Levantino
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise. ISCAS 2013: 173-176 - [c24]Andrea Fenaroli, Salvatore Levantino
Background adaptive linearization of high-speed digital-to-analog Converters. ISCAS 2013: 582-585 - [c23]Giovanni Marucci, Salvatore Levantino
An efficient method to compute phase-noise in injection-locked frequency dividers. ISCAS 2013: 1753-1756 - [c22]Federico Pepe
Simulating phase noise induced from cyclostationary noise sources. ISCAS 2013: 2686-2689 - 2012
- [j30]Giovanni Marzin, Salvatore Levantino
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. IEEE J. Solid State Circuits 47(12): 2974-2988 (2012) - [j29]Andrea Bonfanti
Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1418-1430 (2012) - [j28]Salvatore Levantino
Efficient Calculation of the Impulse Sensitivity Function in Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 628-632 (2012) - [c21]Giovanni Marzin, Salvatore Levantino
A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power. ISSCC 2012: 342-344 - 2011
- [j27]Marco Zanuso, Salvatore Levantino
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. IEEE J. Solid State Circuits 46(3): 627-638 (2011) - [j26]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino
A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power. IEEE J. Solid State Circuits 46(12): 2745-2758 (2011) - [j25]Davide Tasca, Marco Zanuso, Salvatore Levantino
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 200-204 (2011) - [c20]Paolo Maffezzoni, Salvatore Levantino
Behavioral phase-noise analysis of charge-pump phase-locked loops. ECCTD 2011: 357-360 - [c19]Carlo Samori
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. ISCAS 2011: 418-421 - [c18]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. ISSCC 2011: 88-90 - 2010
- [j24]Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita:
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. 2010 (2010) - [j23]Marco Zanuso, Paolo Madoglio, Salvatore Levantino
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 548-555 (2010) - [j22]Salvatore Levantino
Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 671-675 (2010) - [c17]Marco Zanuso, Salvatore Levantino
Time-to-digital converter with 3-ps resolution and digital linearization algorithm. ESSCIRC 2010: 262-265 - [c16]Salvatore Levantino
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. ISSCC 2010: 50-51 - [c15]Marco Zanuso, Salvatore Levantino
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. ISSCC 2010: 476-477
2000 – 2009
- 2009
- [j21]Marco Zanuso, Davide Tasca, Salvatore Levantino
Noise Analysis and Minimization in Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 835-839 (2009) - [c14]Marco Zanuso, Salvatore Levantino
A glitch-corrector circuit for low-spur ADPLLs. ICECS 2009: 595-598 - [c13]Salvatore Levantino
An all-digital architecture for low-jitter regulated delay lines. ICECS 2009: 603-606 - 2008
- [j20]Luigi Panseri, Luca Romanò, Salvatore Levantino
Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter. IEEE J. Solid State Circuits 43(5): 1274-1286 (2008) - [j19]Andrea Bonfanti
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS. IEEE J. Solid State Circuits 43(6): 1403-1413 (2008) - [j18]Alfio Zanchi, Carlo Samori
Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(2): 522-534 (2008) - 2007
- [j17]Paolo Madoglio, Marco Zanuso, Salvatore Levantino
Quantization Effects in All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs 54-II(12): 1120-1124 (2007) - [c12]Andrea Bonfanti
A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN. ESSCIRC 2007: 480-483 - 2006
- [j16]Luca Romanò, Andrea Bonfanti
5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS. IEEE J. Solid State Circuits 41(11): 2457-2467 (2006) - [j15]Andrea Bonfanti
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(3): 481-488 (2006) - [j14]Luca Romanò, Luigi Panseri, Carlo Samori
Matching requirements in LINC transmitters for OFDM signals. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(7): 1572-1578 (2006) - [j13]Luca Romanò, Salvatore Levantino
Multiphase LC oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(7): 1579-1588 (2006) - [c11]Luigi Panseri, Luca Romanò, Salvatore Levantino
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter. CICC 2006: 133-136 - 2004
- [j12]Stefano Pellerano, Salvatore Levantino
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. IEEE J. Solid State Circuits 39(2): 378-383 (2004) - [j11]Salvatore Levantino
Phase noise in digital frequency dividers. IEEE J. Solid State Circuits 39(5): 775-784 (2004) - [j10]Salvatore Levantino
Fast-switching analog PLL with finite-impulse response. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(9): 1697-1701 (2004) - [c10]Luca Romanò, Vita Minerva, Silvia Cavalieri d'Oro, Carlo Samori, Marco Politi:
5-GHz in-phase coupled oscillators with 39% tuning range. CICC 2004: 269-272 - [c9]Luca Romanò, Carlo Samori, Salvatore Levantino, Andrea Bonfanti, Andrea L. Lacaita:
A multi-tank LC-oscillator [microwave oscillator example]. ICECS 2004: 29-32 - [c8]Salvatore Levantino, Andrea Bonfanti, Luca Romanò, Carlo Samori, Andrea L. Lacaita:
Differential tuning oscillators with reduced flicker noise upconversion. ICECS 2004: 33-36 - [c7]Luca Romanò, Salvatore Levantino, Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita:
Phase noise and accuracy in quadrature oscillators. ISCAS (1) 2004: 161-164 - [c6]Salvatore Levantino, Luca Romanò, Carlo Samori, Andrea L. Lacaita:
Fast-switching analog PLL with finite-impulse response. ISCAS (4) 2004: 165-168 - 2003
- [j9]Salvatore Levantino
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing. IEEE J. Solid State Circuits 38(6): 895-904 (2003) - [j8]Sander L. J. Gierkink, Salvatore Levantino
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling. IEEE J. Solid State Circuits 38(7): 1148-1154 (2003) - [j7]Andrea Bonfanti
A DDS-based PLL for 2.4-GHz frequency synthesis. IEEE Trans. Circuits Syst. II Express Briefs 50(12): 1007-1010 (2003) - [c5]Andrea Giovanni Bonfanti
A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application. ESSCIRC 2003: 695-698 - 2002
- [j6]Carlo Samori
Integrated LC oscillators for frequency synthesis in wireless applications. IEEE Commun. Mag. 40(5): 166-171 (2002) - [j5]Salvatore Levantino
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. IEEE J. Solid State Circuits 37(8): 1003-1011 (2002) - [j4]Pietro Andreani, Andrea Bonfanti
Analysis and design of a 1.8-GHz CMOS LC quadrature VCO. IEEE J. Solid State Circuits 37(12): 1737-1747 (2002) - 2001
- [j3]Alfio Zanchi, Carlo Samori
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. IEEE J. Solid State Circuits 36(4): 611-619 (2001) - [c4]Carlo Samori, Salvatore Levantino, Vito Boccuzzi:
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications. CICC 2001: 201-204 - [c3]Alfio Zanchi, Andrea Bonfanti, Salvatore Levantino
Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO. CICC 2001: 209-212 - 2000
- [j2]Carlo Samori
Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's. IEEE J. Solid State Circuits 35(1): 96-99 (2000) - [j1]Franco Zappa
An integrated active-quenching circuit for single-photon avalanche diodes. IEEE Trans. Instrum. Meas. 49(6): 1167-1175 (2000) - [c2]Salvatore Levantino, Alfio Zanchi, Andrea Bonfanti, Carlo Samori:
Fast simulation techniques for phase noise analysis of oscillators. ISCAS 2000: 156-159
1990 – 1999
- 1998
- [c1]Carlo Samori
Design Issues of LC Tuned Oscillators for Integrated Transceivers. Great Lakes Symposium on VLSI 1998: 264-269
Coauthor Index
Andrea Bonfanti
aka: Andrea Giovanni Bonfanti
aka: Andrea Giovanni Bonfanti
Andrea L. Lacaita
aka: Andrea Leonardo Lacaita
aka: Andrea Leonardo Lacaita
[j57] [c59] [c58] [c57] [c55] [j55] [j54] [j53] [c54] [c53] [c52] [j52] [j51] [j50] [j49] [j48] [c51] [c49] [c45] [c44] [c43] [j45] [c42] [c41] [j43] [j42] [j41] [c39] [c38] [j40] [c36] [c31] [j37] [c29] [c28] [j33] [j32] [c26] [c24] [c22] [j30] [j29] [j28] [c21] [j27] [j26] [j25] [c20] [c19] [c18] [j24] [j23] [j22] [c17] [c16] [c15] [j21] [c14] [c13] [j20] [j17] [c12] [j16] [j15] [j14] [j13] [c11] [j12] [j11] [j10] [c9] [c8] [c7] [c6] [j7] [c5] [j6] [j5] [j3] [c3] [j2] [c1]
[j57] [c59] [c58] [c57] [c55] [j55] [j54] [j53] [c54] [c53] [c52] [j52] [j51] [j50] [j49] [j48] [c51] [c50] [c49] [c48] [j47] [j46] [c47] [c44] [c43] [j45] [j44] [c42] [c41] [j43] [j42] [j41] [c40] [c39] [c38] [j40] [j39] [j38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [j37] [j36] [j34] [c29] [c28] [j33] [j32] [j31] [c27] [c26] [c25] [c24] [c23] [c22] [j30] [j28] [c21] [j27] [j26] [j25] [c20] [c19] [c18] [j24] [j23] [j22] [c17] [c16] [c15] [j21] [c14] [c13] [j20] [j17] [j16] [j15] [j13] [c11] [j12] [j11] [j10] [c9] [c8] [c7] [c6] [j9] [j8] [c5] [j6] [j5] [j3] [c4] [c3] [j2] [c2]
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last updated on 2024-12-17 20:59 CET by the dblp team
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