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Chia-Tung Ho
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2020 – today
- 2024
- [c10]Wei Li
, Rongjian Liang
DGR: Differentiable Global Router. DAC 2024: 303:1-303:6 - [c9]Chia-Tung Ho
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation. ISPD 2024: 195-203 - [c8]Rongjian Liang
ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis. MLCAD 2024: 8:1-8:7 - [i3]Chia-Tung Ho, Haoxing Ren:
Large Language Model (LLM) for Standard Cell Layout Design Optimization. CoRR abs/2406.06549 (2024) - [i2]Chia-Tung Ho, Haoxing Ren, Brucek Khailany:
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool. CoRR abs/2408.08927 (2024) - 2023
- [c7]Chia-Tung Ho
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. ISPD 2023: 44-52 - 2022
- [b1]Chia-Tung Ho:
Novel Computer Aided Design (CAD) Methodology for Emerging Technologies to Fight the Stagnation of Moore's Law. University of California, San Diego, USA, 2022 - [j5]Chung-Kuan Cheng
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. IEEE Access 10: 65971-65981 (2022) - [j4]Chung-Kuan Cheng
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1059-1072 (2022) - [c6]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz:
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. ASP-DAC 2022: 288-293 - [i1]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz:
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. CoRR abs/2210.14259 (2022) - 2021
- [j3]Daeyeal Lee
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2142-2155 (2021) - [j2]Chung-Kuan Cheng
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1178-1191 (2021) - [c5]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin:
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning. SLIP 2021: 8-15 - 2020
- [c4]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park:
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. ICCAD 2020: 158:1-158:8
2010 – 2019
- 2019
- [c3]Chia-Tung Ho, Andrew B. Kahng:
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. ICCAD 2019: 1-8 - 2017
- [j1]Yu-Min Lee
InTraSim: Incremental Transient Simulation of Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2052-2065 (2017) - 2014
- [c2]Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng:
Incremental transient simulation of power grid. ISPD 2014: 93-100 - 2013
- [c1]Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng:
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. VLSI-DAT 2013: 1-4
Coauthor Index
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