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Cyrus Bamji
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2000 – 2009
- 2004
- [c17]S. Burak Gokturk, Hakan Yalcin, Cyrus Bamji:
A Time-Of-Flight Depth Sensor - System Description, Issues and Solutions. CVPR Workshops 2004: 35 - 2001
- [j3]Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
Fast and accurate timing characterization using functionalinformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 315-331 (2001) - [j2]Yanbin Jiang, Sachin S. Sapatnekar
, Cyrus Bamji:
Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 577-589 (2001) - [c16]Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
An Advanced Timing Characterization Method Using Mode Dependency. DAC 2001: 657-660 - 2000
- [c15]Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin:
Transistor-Level Timing Analysis Using Embedded Simulation. ICCAD 2000: 344-348
1990 – 1999
- 1999
- [c14]Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah:
Functional Timing Analysis for IP Characterization. DAC 1999: 731-736 - 1998
- [j1]Yanbin Jiang, Sachin S. Sapatnekar
Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 625-633 (1998) - [c13]Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim:
Combined transistor sizing with buffer insertion for timing optimization. CICC 1998: 605-608 - [c12]Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji:
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. ICCD 1998: 276-281 - [c11]Cyrus Bamji, Ravi Varadarajan:
Incremental Autojogging using Range Spaces. VLSI Design 1998: 265- - [c10]Cyrus Bamji, Manjit Borah:
An Improved Cost Heuristic for Transistor Sizing. VLSI Design 1998: 534- - 1997
- [c9]Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar:
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD 1997: 130-135 - 1996
- [c8]Cyrus Bamji, Enrico Malavasi:
Enhanced Network Flow Algorithm for Yield Optimization. DAC 1996: 746-751 - 1994
- [c7]Cyrus Bamji, Jonathan Allen:
GLOVE: A Graph-Based Layout Verifier. VLSI Design 1994: 215-220 - 1993
- [c6]Cyrus Bamji, Ravi Varadarajan:
MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction. DAC 1993: 389-394 - 1992
- [c5]Cyrus Bamji, Ravi Varadarajan:
Hierarchical Pitchmatching Compaction Using Minimum Design. DAC 1992: 311-317 - [c4]Ravi Varadarajan, Cyrus Bamji:
Cloning techniques for hierarchical compaction. ICCAD 1992: 158-161
1980 – 1989
- 1989
- [b1]Cyrus Bamji:
Graph-based representations and coupled verification of VLSI schematics and layouts. Massachusetts Institute of Technology, Cambridge, MA, USA, 1989 - [c3]Cyrus Bamji, Jonathan Allen:
GRASP: A Grammar-based Schematic Parser. DAC 1989: 448-453 - 1985
- [c2]Cyrus Bamji, Charles E. Hauck, Jonathan Allen:
A design by example regular structure generator. DAC 1985: 16-22 - [c1]Charles E. Hauck, Cyrus Bamji, Jonathan Allen:
The systematic exploration of pipelined array multiplier performance. ICASSP 1985: 1461-1464
Coauthor Index
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