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Grzegorz Pastuszak
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- affiliation: Warsaw University of Technology, Poland
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2020 – today
- 2021
- [j15]Grzegorz Pastuszak
, Adam Skowyrski
Quantifier elimination theory and maps which preserve semipositivity. Quantum Inf. Process. 20(3): 123 (2021) - 2020
- [j14]Grzegorz Pastuszak
Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 891-902 (2020) - [j13]Grzegorz Pastuszak
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2573-2583 (2020)
2010 – 2019
- 2016
- [j12]Grzegorz Pastuszak
Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder. J. Real Time Image Process. 11(4): 663-673 (2016) - [j11]Grzegorz Pastuszak
Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder. J. Real Time Image Process. 12(2): 517-529 (2016) - [j10]Grzegorz Pastuszak
On a Criterion for Simultaneous Block-Diagonalization of Normal Matrices. Open Syst. Inf. Dyn. 23(1): 1650003:1-1650003:12 (2016) - [j9]Grzegorz Pastuszak
Algorithm and Architecture Design of the H.265/HEVC Intra Encoder. IEEE Trans. Circuits Syst. Video Technol. 26(1): 210-222 (2016) - [j8]Grzegorz Pastuszak
Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder. J. Signal Process. Syst. 82(3): 391-402 (2016) - 2015
- [j7]Grzegorz Pastuszak
Flexible Architecture Design for H.265/HEVC Inverse Transform. Circuits Syst. Signal Process. 34(6): 1931-1945 (2015) - [j6]Grzegorz Pastuszak
Hardware architectures for the H.265/HEVC discrete cosine transform. IET Image Process. 9(6): 468-477 (2015) - [j5]Grzegorz Pastuszak
Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization. IEEE Trans. Circuits Syst. Video Technol. 25(11): 1844-1856 (2015) - 2014
- [j4]Mikolaj Roszkowski, Grzegorz Pastuszak
Intra Prediction for the Hardware H.264/AVC High Profile Encoder. J. Signal Process. Syst. 76(1): 11-17 (2014) - [c24]Andrzej Abramowski
A double-path intra prediction architecture for the hardware H.265/HEVC encoder. DDECS 2014: 27-32 - [c23]Mikolaj Roszkowski, Grzegorz Pastuszak
FPGA design of the computation unit for the semi-global stereo matching algorithm. DDECS 2014: 230-233 - [c22]Grzegorz Pastuszak
FPGA architectures of the quantization and the dequantization for video encoders. DDECS 2014: 290-293 - 2013
- [j3]Grzegorz Pastuszak
Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder. IEEE Trans. Circuits Syst. Video Technol. 23(5): 802-812 (2013) - [c21]Grzegorz Pastuszak
Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder. DSD 2013: 423-428 - [c20]Andrzej Abramowski
A Novel Intra Prediction Architecture for the Hardware HEVC Encoder. DSD 2013: 429-436 - 2012
- [c19]Grzegorz Pastuszak
Hardware implementation of adaptive motion estimation and compensation for H.264/AVC. PCS 2012: 369-372 - 2010
- [c18]Mikolaj Roszkowski, Grzegorz Pastuszak:
Intra prediction hardware module for high-profile H.264/AVC decoder. PDeS 2010: 60-65 - [c17]Grzegorz Pastuszak, Michal Wieczorek:
Stream header decoder and context-adaptive variable-length decoder hardware module for H.264/AVC codec. PDeS 2010: 66-71 - [c16]Grzegorz Brzuchalski, Grzegorz Pastuszak:
Hardware implementation of the transformation module of the MPEG-4 AAC standard. PDeS 2010: 205-208 - [c15]Andrzej Abramowski, Grzegorz Pastuszak:
Context-adaptive binary arithmetic decoder architecture for H.264/AVC. PDeS 2010: 211-214 - [c14]Mariusz H. Jakubowski, Grzegorz Pastuszak:
Data Reuse in Two-level Hierarchical Motion Estimation for High Resolution Video Coding. SIGMAP 2010: 159-162
2000 – 2009
- 2009
- [c13]Mariusz H. Jakubowski, Grzegorz Pastuszak:
An Adaptive Computation-aware Algorithm for Multi-frame Variable Block-size Motion Estimation in H.264/AVC. SIGMAP 2009: 122-125 - 2008
- [j2]Grzegorz Pastuszak
A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC. IEEE Trans. Circuits Syst. Video Technol. 18(7): 949-960 (2008) - [c12]Grzegorz Pastuszak
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection. ISVLSI 2008: 203-208 - [c11]Mariusz H. Jakubowski, João Ascenso, Grzegorz Pastuszak:
Constant Bitrate Control for a Distributed Video Coding System. SIGMAP 2008: 131-138 - 2007
- [c10]Grzegorz Pastuszak, Andrzej Pietrasiewicz:
Multi-sequence H.264/AVC Rate Control Based on the Linear Model. ICETE (Selected Papers) 2007: 284-292 - [c9]Andrzej Pietrasiewicz, Grzegorz Pastuszak:
Rate Control for Multi-Sequence H.264/AVC Compression. SIGMAP 2007: 456-461 - [c8]Grzegorz Pastuszak
Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression. SiPS 2007: 175-180 - 2006
- [c7]Grzegorz Pastuszak
Architecture Design for the Context Formatter in the H.264/AVC Encoder. DDECS 2006: 71-72 - [c6]Grzegorz Pastuszak
Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding. PARELEC 2006: 380-385 - [p1]Grzegorz Pastuszak:
A hardware-oriented analysis of arithmetic coding - comparative study of JPEG2000 and H.264/AVC comppression standards. e-Business and Telecommunication Networks 2006: 264-271 - 2005
- [j1]Grzegorz Pastuszak
A high-performance architecture for embedded block coding in JPEG 2000. IEEE Trans. Circuits Syst. Video Technol. 15(9): 1182-1191 (2005) - [c5]Grzegorz Pastuszak
Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder. ICIAP 2005: 604-611 - [c4]Grzegorz Pastuszak
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000. ICME 2005: 225-228 - 2004
- [c3]Grzegorz Pastuszak:
Hardware-Oriented Analysis of the Arithmetic Coding - Comparative Study of JPEG2000 and H.264/AVC Compression Standards. ICETE (3) 2004: 309-316 - [c2]Grzegorz Pastuszak:
A high-performance architecture of arithmetic coder in JPEG2000. ICME 2004: 1431-1434 - [c1]Grzegorz Pastuszak:
A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding. PARELEC 2004: 303-308
Coauthor Index
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