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Tarek Ould Bachir
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2020 – today
- 2024
- [j9]Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria:
PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA. Future Internet 16(9): 307 (2024) - [j8]Ahmed Bouzid, Saad Chidami, Tristan Quentin Lailler, Adrián Carrillo García, Tarek Ould-Bachir, Jamal Chaouki:
Innovative Non-Invasive and Non-Intrusive Precision Thermometry in Stainless-Steel Tanks Using Ultrasound Transducers. Sensors 24(11): 3404 (2024) - [c16]Mostafa Abbasmollaei, Tarek Ould-Bachir, Yvon Savaria:
Normal and Resilient Mode FPGA-based Access Gateway Function Through P4-generated RTL. DRCN 2024: 32-38 - [c15]Florent Allard, Tarek Ould-Bachir, Yvon Savaria:
Enhancing P4 Syntax to Support Extended Finite State Machines as Native Stateful Objects. NetSoft 2024: 326-330 - 2023
- [c14]Yadollah Zamanidoost, Nada Alami-Chentoufi, Tarek Ould-Bachir, Sylvain Martel:
Efficient Region Proposal Extraction of Small Lung Nodules Using Enhanced VGG16 Network Model. CBMS 2023: 483-488 - [c13]El-Mehdi Makhroute, Mohammed-Ayoub Elharti, Vincent Brouillard, Yvon Savaria, Tarek Ould-Bachir:
Implementing and Evaluating a P4-based Access Gateway Function on a Tofino Switch. CommNet 2023: 1-7 - [c12]Thibaut Gravey, Karim Meddah, Téo Robert, Emmanuel Rutovic, Romain Monthéard, Tarek Ould Bachir:
A PYNQ-Based Data Acquisition System for HIL Simulations on Low-Cost FPGAs. ICIT 2023: 1-6 - [c11]Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria:
An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs. ISCAS 2023: 1-5 - 2022
- [j7]Hossein Chalangar, Tarek Ould Bachir, Keyhan Sheshyekani, Jean Mahseredjian:
Methods for the Accurate Real-Time Simulation of High-Frequency Power Converters. IEEE Trans. Ind. Electron. 69(9): 9613-9623 (2022) - [c10]Karim Meddah, Hossein Chalangar, Tarek Ould Bachir:
Real-Time Simulation of a Fast Charger Using a Low-Cost FPGA Platform. IECON 2022: 1-6 - [c9]Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria:
A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. ISCAS 2022: 672-676 - 2021
- [j6]Hossein Chalangar, Tarek Ould Bachir, Keyhan Sheshyekani, Jean Mahseredjian:
A Direct Mapped Method for Accurate Modeling and Real-Time Simulation of High Switching Frequency Resonant Converters. IEEE Trans. Ind. Electron. 68(7): 6348-6357 (2021) - [c8]Andy Gallay, Tarek Ould Bachir:
Implementing Multistage Interconnection Networks on FPGA U sing Chisel Language. CCECE 2021: 1-6 - [c7]Karim Meddah, Tarek Ould Bachir, Mohamed Becherif, Amel Benmouna:
An FPGA-based Real-Time Simulation of a Hybrid Fuel Cell/Battery Source. CCECE 2021: 1-5 - 2020
- [i1]Hossein Chalangar, Tarek Ould Bachir, Keyhan Sheshyekani, Jean Mahseredjian:
A direct mapped method for accurate modeling and real-time simulation of high switching frequency resonant converters. CoRR abs/2006.04155 (2020)
2010 – 2019
- 2019
- [c6]Federico Montano, Tarek Ould-Bachir, Jean Mahseredjian, Jean-Pierre David:
A Low-Latency Reconfigurable Multistage Interconnection Network. CCECE 2019: 1-4 - 2018
- [j5]Federico Montano, Tarek Ould-Bachir, Jean-Pierre David:
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron. 65(1): 636-644 (2018) - 2015
- [j4]Tarek Ould Bachir, Handy Fortin-Blanchette, Kamal Al-Haddad:
A Network Tearing Technique for FPGA-Based Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron. 62(6): 3409-3418 (2015) - [c5]Tarek Ould Bachir, Asma Merdassi, Sébastien Cense, Handy Fortin-Blanchette, Jean Bélanger:
FPGA-based real-time simulation of a PSIM model: An indirect matrix converter case study. IECON 2015: 3336-3340 - 2013
- [j3]Tarek Ould-Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David:
A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits. Math. Comput. Simul. 91: 167-177 (2013) - [j2]Tarek Ould-Bachir, Jean-Pierre David:
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators. ACM Trans. Reconfigurable Technol. Syst. 6(1): 1:1-1:21 (2013) - 2012
- [j1]Hugo Fortin-Blanchette, Tarek Ould-Bachir, Jean-Pierre David:
A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Trans. Ind. Electron. 59(12): 4555-4567 (2012) - [c4]Christian Dufour, Sébastien Cense, Tarek Ould-Bachir, Luc-André Grégoire, Jean Bélanger:
General-purpose reconfigurable low-latency electric circuit and motor drive solver on FPGA. IECON 2012: 3073-3081 - [c3]Tarek Ould-Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David:
Effective floating-point calculation engines intended for the FPGA-based HIL simulation. ISIE 2012: 1363-1368 - 2010
- [c2]Tarek Ould Bachir, Jean-Pierre David:
Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision. FCCM 2010: 105-108
2000 – 2009
- 2009
- [c1]Tarek Ould Bachir, Jean-Jules Brault:
FPGA-driven pseudorandom number generators aimed at accelerating Monte Carlo methods. AICCSA 2009: 989-996
Coauthor Index
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