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"A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based ..."

Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria (2022)

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DOI: 10.1109/ISCAS48785.2022.9937607

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

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Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria:
A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. ISCAS 2022: 672-676

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