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ICCD 1988: Rye Brook, NY, USA
- Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988. IEEE 1988, ISBN 0-8186-0872-2
- Randall J. Brouwer, Prithviraj Banerjee:
A parallel simulated annealing algorithm for channel routing on a hypercube multiprocessor. 4-7 - James H. Kukula:
Object relocation in OX. 8-10 - Susheel J. Chandra, Janak H. Patel:
Test generation in a parallel processing environment. 11-14 - Harold Dozier, Jeff Gruger:
Super computer technology at Convex. 16-20 - Stephen A. Bowen:
The Cray Y-MP-a VLSI supercomputer. 21-23 - Donald R. Mullen, Geoffrey Fernald:
The design of a reduced ambient temperature, air cooled supercomputer. 24-29 - P. Sadayappan, V. Visvanathan:
Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization. 32-35 - H. V. Jagadish:
Sorting on an array of processors. 36-39 - Joseph R. Cavallaro, Franklin T. Luk:
Floating point CORDIC for matrix computations. 40-42 - Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley:
Analog circuit synthesis and exploration in OASYS. 44-47 - Antony H. Fung, David J. Chen, Ying-Nan Lai, Bing J. Sheu:
Knowledge-based analog circuit synthesis with flexible architecture. 48-51 - D. Zhou, Franco P. Preparata, S. M. Kang:
Interconnection delay in very high-speed VLSI. 52-55 - Vishwani D. Agrawal, Hassan Farhat, Sharad Seth:
Test generation by fault sampling. 58-61 - Antonio Lioy:
Adaptative backtrace and dynamic partitioning enhance ATPG. 62-65 - Wu-Tung Cheng:
The BACK algorithm for sequential test generation. 66-69 - Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
:
Random testability analysis: comparing and evaluating existing approaches. 70-73 - Clinton C. Chao, Kim H. Chen, Ravi Kaw, Jacques Leibovitz, V. K. Nagesh, Kenneth D. Scholz:
Multi-chip packaging for high performance systems. 76-81 - Olgierd A. Palusinski, Andreas C. Cangellaris, John L. Prince, J. C. Liao, L. Vakanis:
Modeling and simulation of coupled lossy lines for VLSI interconnections. 82-86 - Andrew T. Yang, D. S. Gao, S. M. Kang:
Computer-aided simulation of optical interconnects for high-speed digital systems. 87-90 - Jürgen Jahns:
Free-space optical crossover interconnects for parallel computers. 91-94 - Seth Abraham, Krishnan Padmanabhan:
Instruction reorganization for a variable-length pipelined microprocessor. 96-101 - Tadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada:
Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor. 102-105 - Kanad Ghose, Robert M. Stewart:
The capability mechanism of a VLSI processor. 106-109 - D. K. Lewis, J. P. Costello, D. M. O'Connor:
Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor. 110-113 - Rakesh Chadha, Chin-Fu Chen:
Extension of a transistor level digital timing simulator to include first order analog behavior. 116-119 - A. C. J. Stroucken, G. J. J. M. van de Ven:
MILES: a mixed level simulator for analog/digital design. 120-123 - Charles A. Zukowski, De-Ping Chen:
Variable reduction in MOS timing models. 124-128 - Chien-Chih Chen, Yu-Hen Hu:
Parallel LU factorization for circuit simulation on an MIMD computer. 129-132 - Mohsine Eleuldj, El Mostapha Aboulhamid, Eduard Cerny:
A class of fault-tolerant cellular permutation networks. 136-139 - Chin-Long Wey, Sin-Min Chang:
Test generation of C-testable array dividers. 140-144 - William P. Marnane, Will R. Moore:
Testing of VLSI regular arrays. 145-148 - Cees Niessen, Kees van Berkel, Martin Rem, Ronald W. J. J. Saeijs:
VLSI programming and silicon compilation; a novel approach from Philips research. 150-151 - Kees van Berkel, Martin Rem, Ronald W. J. J. Saeijs:
VLSI programming. 152-156 - Kees van Berkel, Ronald W. J. J. Saeijs:
Compilation of communicating processes into delay-insensitive circuits. 157-162 - Ronald W. J. J. Saeijs, Kees van Berkel:
The design of the VLSI image-generator ZaP. 163-166 - C. C. Chi, D. Grischkowsky:
Tera-Hertz study of normal and superconducting transmission lines. 168-171 - Mehdi Hatamian, Larry A. Hornak, Stuart K. Tewksbury:
Potential applications of high-Tc superconducting transmission lines in integrated systems. 172-177 - Frédéric Mailhot, Giovanni De Micheli:
Automatic layout and optimization of static CMOS cells. 180-185 - D. P. Dutt, G. Lakhani:
Optimization for automatic cell assembly. 186-189 - Paul K. Sun:
An octagonal geometry compactor. 190-193 - J. Kelly Flanagan, Brent E. Nelson:
Processor design using path programmable logic. 196-199 - Liliana Díaz-Olavarrieta, Safwat G. Zaky:
Direct synthesis of mapping circuits. 200-203 - Donald F. Hooper Jr.:
SID: synthesis of integral design. 204-208 - Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko:
The KARL/KARATE system - integrating functional test development into a CAD environment for VLSI. 209-212 - Mark Birman, George Chu, Larry Hu, John McLeod, N. Bedard, F. Ware, L. Torban, C. M. Lim:
Design of a high-speed arithmetic datapath. 214-215 - King Fai Pang, Hsui-Wei Soong, Randal Sexton, Peng-Huat Ang:
Generation of high speed CMOS multiplier-accumulators. 217-220 - Gary Bewick, Paul Song, Giovanni De Micheli, Michael J. Flynn:
Approaching a nanosecond: a 32 bit adder. 221-226 - Mary Jane Irwin, Robert Michael Owens:
A comparison of two digit serial VLSI adders. 227-229 - Sidi Yom Tov, Benjamin Maytal, Z. Bikovsky, Dan Biran, Jonathan Levy II, Y. Milstain, A. Ostrer:
System interface of the NS32532 microprocessor. 232-235 - Paul L. Borrill:
Limits of backplane bus design. 236-239 - Paul Sweazey:
VLSI support for copyback caching protocols on Futurebus. 240-246 - Chaim Bendelac, Gady Erlich:
CTP-A family of optimizing compilers for the NS32532 microprocessor. 247-250 - Robert Lisanke, Franc Brglez, Gershon Kedem:
McMAP: a fast technology mapping procedure for multi-level logic synthesis. 252-256 - Mario C. Lega:
Mapping properties of multi-level logic synthesis operations. 257-261 - J. Ishikawa, H. Sato, M. Hiramine, Kasumi Ishida, S. Oguri, Y. Kazuma, S. Murai:
A rule based logic reorganization system LORES/EX. 262-266 - Rainer Amann, Bernhard Eschermann, Utz G. Baitinger:
PLA based finite state machines using Johnson counters as state memories. 267-270 - P. Duba, Ravi K. Iyer:
Transient fault behavior in a microprocessor - A case study. 272-276 - Brian L. Shing, Mark A. Franklin:
Classical fault analysis for MOS VLSI circuits. 277-282 - Niraj K. Jha:
A new class of symmetric error correcting / unidirectional error detecting codes. 283-286 - T. Iizuka, T. Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, T. Miyoshi:
Large memory embedded ASICs. 292-295 - Conrad J. Dell'Oca:
Gate array technology. 296-299 - Michael Schlansker, Michael McNamara:
The CydraTM 5 computer system architecture. 302-306 - James E. Smith, Gregory E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon:
The Astronautics ZS-1 processor. 307-310 - Pieter S. van der Meulen, Ming-Der Huang, Uzi Bar-Gadda, Eva Lee, Peter G. M. Baltus:
EXIST: an interactive VLSI architectural environment. 312-319 - Kathleen M. Nichols, John T. Edmark:
PARET: an integrated visual tool for the study of parallel systems. 320-323 - Rick L. Spickelmier, A. Richard Newton:
Critic: a knowledge-based program for critiquing circuit designs. 324-327 - Lee Whetsel:
A proposed standard test bus and boundary scan architecture. 330-333 - Jon Turino:
IEEE P1149 Proposed Standard Testability Bus - An update with case histories. 334-337 - Brian R. Wilkins:
HIT: a standard constructional system for testability and maintainability. 338-341 - Thaddeus J. Gabara, David W. Thompson:
High speed, low power CMOS transmitter-receiver system. 344-347 - William E. Engeler, Menahem Lowy, John Pedicone, John Bloomer, James Richotte, David Chan:
A high speed static CMOS PLA architecture. 348-351 - Charles A. Zukowski, Kevin Shum:
A matched-delay CMOS TDM multiplexer cell. 352-355 - Junien Labrousse, Gerrit A. Slavenburg:
CREATE-LIFE: a design system for high performances VLSI circuits. 356-360 - Glenn Hinton, Konrad Lai, Randy Steck:
Microarchitecture of the 80960 high-integration processors. 362-365 - Tom Riordan, G. P. Grewal, Simon Hsu, John Kinsel, Jeff Libby, Roger March, Marvin Mills, Paul Ries, Randy Scofield:
The MIPS M2000 system. 366-369 - Charles Melear:
RISC architecture of the M88000. 370-373 - Masood Namjoo:
First 32-bit SPARC-based processors implemented in high-speed CMOS. 374-376 - Joseph Lis, Daniel D. Gajski:
Synthesis from VHDL. 378-381 - Sally A. Hayati, Alice C. Parker, John J. Granacki:
Representation of control and timing behavior with applications to interface synthesis. 382-387 - N. S. H. Brooks, R. J. Mack:
A novel approach to the synthesis of practical datapath architectures using artificial intelligence techniques. 388-391 - Kholdoun Torki
UBIST version of the SYCO's control section compiler. 392-396 - Catherine H. Gebotys, Mohamed I. Elmasry:
Integrated design and test synthesis. 398-401 - J. R. Miles, Anthony P. Ambler, K. A. E. Totton:
Estimation of area and performance overheads for testable VLSI circuits. 402-407 - Franc Brglez, David Bryan, John D. Calhoun, Robert Lisanke:
A modular scan-based testability system. 408-412 - Morten Toverud, Vidar Andersen:
CESAR - A programmable high performance systolic array processor. 414-417 - Krishna P. Belkhale, Prith Banerjee:
Reconfiguration strategies in VLSI processor arrays. 418-421 - Sabine Bauer, Uwe Schwiegelshohn
Parallel calculation of shortest paths in sparse graphs on a systolic array. 422-425 - Tom Shiple, Paul Kollaritsch, Derek Smith, Jonathan Allen:
Area evaluation metrics for transistor placement. 428-433 - Rathin Putatunda, David Smith, Michael Stebnisky, Carl Puschak, Paul Patent:
VITAL: fully automatic placement strategies for very large semicustom designs. 434-439 - Dwight D. Hill:
Alternative strategies for applying min-cut to VLSI placement. 440-444 - A. C. Erdal, Pierre A. Uszynski:
A global chip test implementation including built-in self-test. 446-449 - Jing-Yang Jou:
A testable PLA design with low overhead and ease of test generation. 450-453 - Derek Feltham, Phil Nigh, L. Richard Carley, Wojciech Maly:
Current sensing for built-in testing of CMOS circuits. 454-457 - Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò:
Aliasing errors in signature analysis testing of integrated circuits. 458-461 - Danny F. Newport, H. M. Dent, M. E. Casey, Donald W. Bouldin:
A modular VLSI architecture for coincidence detection in positron emission tomography. 464-467 - W. Marwood, A. P. Clarke:
A co-processor with supercomputer capabilities for personal computers. 468-471 - J. Robert Heath, Eric Allen Disch:
A methodology for the control and custom VLSI implementation of large-scale Clos networks. 472-477 - Stephen A. Ward, Robert C. Zak:
Set-associative dynamic random access memory. 478-483 - Milos D. Ercegovac, Tomás Lang, Ramin Modiri:
Implementation of fast radix-4 division with operands scaling. 486-489 - Luigi Dadda, Luca Breveglieri:
A serial-input serial-output bit-sliced convolver. 490-495 - Vincenzo Piuri, Renato Stefanelli:
Use of redundant binary representation for fault-tolerant arithmetic array processors. 496-501 - Alexander Skavantzos, Fred J. Taylor:
Parallel decomposition of multipliers modulo (2n±1). 502-506 - B. Sharma, Rajiv Jain, Melvin A. Breuer, Alice C. Parker, Cauligi S. Raghavendra, C. Y. Tseng:
The POTATO chip architecture: a study in tradeoffs for signal processing chip design. 508-513 - Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra:
Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor. 514-519 - Irving S. Reed, B. Sharma, Ming-Tang Shih, John Bailey, Trieu-Kien Truong:
VLSI implementation of GSC architecture with a new ripple carry adder. 520-523 - Robert F. Miracky, A. Hartmann, L. N. Smith, S. Redfield, U. Ghoshal, B. Weigler:
Design of a 64-processor by 128-memory crossbar switching network. 526-532 - Khai-Quang Luc, Shauchi Ong, Elbert C. Hu:
Trace driven modelling and performance evaluation of tightly coupled multiprocessor systems. 533-536 - Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec:
A highly parallel processor with an instruction set including relational algebra. 537-538 - Roger D. Chamberlain, Mark N. Edelman, Mark A. Franklin, Ellen E. Witte:
Simulated annealing on a multiprocessor. 540-544 - Rajeev Jayaraman, Frederica Darema:
Error tolerance in parallel simulated annealing techniques. 545-548 - Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken:
Stop criteria in simulated annealing. 549-552 - S. H. Hosseini:
On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors. 554-559 - Stephen Pateras, Janusz Rajski:
A self-reconfiguration scheme for fault-tolerant VLSI processor arrays. 560-563 - Fausto Distante, Fabrizio Lombardi, Donatella Sciuto:
Array partitioning: a methodology for reconfigurability and reconfiguration problems. 564-567 - Fausto Distante, Vincenzo Piuri:
APES: an integrated system for behavioral design, simulation and evaluation of array processors. 568-572 - Chip C. Stearns, Daniel Luthi, Peter A. Ruetz, Peng H. Ang:
Design of a 20 MHz 64-tap transversal filter. 574-577 - Shannon Shen, Surendar Magar, Raul Aguilar, Gerry Luikuo, Mike Fleming, K. Rishavy, K. Murphy, C. Furman:
A high performance CMOS chipset for FFT processors. 578-581 - Seong-Mo Park, Winser E. Alexander, Jung H. Kim, William E. Batchelor, William T. Krakow:
A novel VLSI architecture for the real-time implementation of 2-D signal processing systems. 582-585 - T. A. Misko:
A GaAs vector memory system for signal processing. 586-589 - Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto:
A functional approach to formal hardware verification: the MTI experience. 592-595 - Atsushi Takahara, Takashi Nanya:
A higher level hardware design verification. 596-599 - Michael P. Fourman, W. J. Palmer, R. M. Zimmer:
Proof and synthesis. 600-603 - Shiu-Kai Chin, Kevin J. Greene:
Verifiable and executable theories of design for synthesizing correct hardware. 604-610 - William J. Nohilly:
ES/3090: a realization of ESA/370 system architecture in IBM's most powerful mainframe computer through a balance of technology and system innovations. 611-614
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