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ICCAD 1989: Santa Clara, California, USA
- 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers. IEEE Computer Society 1989, ISBN 0-8186-1986-4
- Todd P. Kelsey, Kewal K. Saluja:
Fast test generation for sequential circuits. 345-347 - Charles C. Chiang, Majid Sarrafzadeh, Chak-Kuen Wong:
A powerful global router: based on Steiner min-max trees. 2-5 - Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong:
Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree. 6-9 - Andranik Mirzaian:
A minimum separation algorithm for river routing with bounded number of jogs. 10-13 - Nohbyung Park, Fadi J. Kurdahi:
Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths. 16-19 - Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin:
A new integer linear programming formulation for the scheduling problem in data path synthesis. 20-23 - Ki Soo Hwang, Albert E. Casavant, Ching-Tang Chang, Manuel A. d'Abreu:
Scheduling and hardware sharing in pipelined data paths. 24-27 - Jean Christophe Madre, Olivier Coudert, Jean-Paul Billon:
Automating the diagnosis and the rectification of design errors with PRIAM. 30-33 - Susheel J. Chandra, Janak H. Patel:
Accurate logic simulation in the presence of unknowns. 34-37 - J. Lawrence Carter, Barry K. Rosen, Gordon L. Smith, Vijay Pitchumani:
Restricted symbolic evaluation is fast and useful. 38-41 - Sabih H. Gerez
, Otto E. Herrmann:
CRACKER: a general area router based on stepwise reshaping. 44-47 - Mark A. Mostow:
AGAR: a single-layer router for gate array cell generation. 48-51 - Tai-Ming Parng, Ren-Song Tsay:
A new approach to sea-of-gates global routing. 52-55 - David W. Knapp:
Manual rescheduling and incremental repair of register-level datapaths. 58-61 - Kazutoshi Wakabayashi, Takeshi Yoshimura:
A resource sharing and control synthesis method for conditional branches. 62-65 - Thomas E. Dillinger, Kathy M. McCarthy, Thomas A. Mosher, Dale R. Neumann, Randall A. Schmidt:
A logic synthesis system for VHDL design descriptions. 66-69 - Hau-Yung Chen, Santanu Dutta:
A timing model for static CMOS gates. 72-75 - Sungho Kim, Prithviraj Banerjee:
An accurate timing model for fault simulation in MOS circuits. 76-79 - Bryan D. Ackland, Robert A. Clark:
Event-EMU: an event driven timing simulator for MOS VLSI circuits. 80-83 - David Overhauser, Ibrahim N. Hajj, Yi-Fan Hsu:
Automatic mixed-mode timing simulation. 84-87 - Ying-Meng Li, Pushan Tang:
Global refinement for building block layout. 90-93 - Malgorzata Marek-Sadowska, Shen Lin:
Timing driven placement. 94-97 - Bernhard Korte, Hans Jürgen Prömel, Angelika Steger:
Combining partitioning and global routing in sea-of-cells design. 98-101 - Miles Murdocca:
Layout methods for digital optical computing. 102-105 - Stefaan Note, Francky Catthoor, Jef L. van Meerbergen, Hugo De Man:
Definition and assignment of complex data-paths suited for high throughput applications. 108-111 - Richard I. Hartley, Albert E. Casavant:
Tree-height minimization in pipelined architectures. 112-115 - Douglas M. Grant, Peter B. Denyer, I. Finlay:
Synthesis of address generators. 116-119 - Larry M. Augustin:
Timing models in VAL/VHDL. 122-125 - Ankan K. Pramanick, Sudhakar M. Reddy:
On the computation of the ranges of detected delay fault sizes. 126-129 - Carl-Johan H. Seger:
A bounded delay race model. 130-133 - Xiao-Ming Xiong:
Two-dimensional compaction for placement refinement. 136-139 - P. Gee, Ibrahim N. Hajj, Sung-Mo Kang:
A custom cell generation system for double-metal CMOS technology. 140-143 - Richard Anderson, Simon Kahan, Martine D. F. Schlag:
An O(n log n) algorithm for 1-D tile compaction. 144-147 - R. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu:
An efficient algorithm for layout compaction problem with symmetry constraints. 148-151 - Phil Nigh, Wojciech Maly:
Layout-driven test generation. 154-157 - Hideo Fujiwara, Tomoo Inoue:
Optimal granularity of test generation in a distributed system. 158-161 - Samy Makar, Edward J. McCluskey:
The critical path for multiple faults. 162-165 - Hector R. Sucar, Susheel J. Chandra, David J. Wharton:
High performance test generation for accurate defect models in CMOS gate array technology. 166-169 - F. T. Hady, James H. Aylor, Ronald D. Williams, Ronald Waxman:
Uninterpreted modeling using the VHSIC hardware description language (VHDL). 172-175 - Ramón D. Acosta, Steven P. Smith, Jeff Larson:
Mixed-mode simulation of compiled VHDL programs. 176-179 - Alec G. Stanculescu, Andy S. Tsay, Alex N. D. Zamfirescu, D. L. Perry:
Switch-level VHDL descriptions. 180-183 - Balsha R. Stanisic, Mark W. Brown:
VHDL modeling for analog-digital hardware designs (VHSIS hardware description language). 184-187 - Tat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch:
An efficient method for parametric yield optimization of MOS integrated circuits. 190-193 - K. K. Low, Stephen W. Director:
A new methodology for the design centering of IC fabrication processes. 194-197 - Nicolas Salamina, Mark R. Rencher:
Statistical bipolar circuit design using MSTAT. 198-201 - Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
Computation of bus current variance for reliability estimation of VLSI circuits. 202-205 - Srinivas Devadas, Kurt Keutzer:
Boolean minimization and algebraic factorization procedures for fully testable sequential machines. 208-211 - Kwang-Ting Cheng, Vishwani D. Agrawal:
State assignment for initializable synthesis (gate level analysis). 212-215 - Pranav Ashar, Srinivas Devadas, A. Richard Newton:
Optimum and heuristic algorithms for finite state machine decomposition and partitioning. 216-219 - Michael Bolotski, Daniel Camporese, Rod Barman:
State assignment for multilevel logic using dynamic literal estimation. 220-223 - Vijay P. Kumar, Anton T. Dahbura, Fred Fischer, Patrick Juola:
An approach for the yield enhancement of programmable gate arrays. 226-229 - Phill-Kyu Rhee, Jung Hwan Kim, Hee Yong Youn:
A novel reconfiguration scheme for 2-D processor arrays. 230-233 - Kuochen Wang, Sy-Yen Kuo:
Fault detection and location in reconfigurable VLSI arrays. 234-237 - Ming-Feng Chang, Weiping Shi, W. Kent Fuchs:
Optimal wafer probe testing and diagnosis of k-out-of-n structures. 238-241 - Dae-Hyung Cho, Tae-Han Kim, Jeong-Taek Kong:
A table look-up model using a 3-D isoparametric shape function with improved convergency. 244-247 - Chandramouli Visweswariah, Ronald A. Rohrer:
Piecewise approximate circuit simulation. 248-251 - Tuyen V. Nguyen, Peter Feldmann, Stephen W. Director, Ronald A. Rohrer:
SPECS simulation validation with efficient transient sensitivity computation. 252-255 - Rao Prakash Pokala, Dileep A. Divekar:
Thermal analysis in SPICE. 256-259 - Erik Brunvand, Robert F. Sproull:
Translating concurrent programs into delay-insensitive circuits. 262-265 - Steven M. Nowick, David L. Dill:
Practicality of state-machine verification of speed-independent circuits. 266-269 - Derek C. Wong, Giovanni De Micheli, Michael J. Flynn:
Inserting active delay elements to achieve wave pipelining. 270-273 - Anoop Singhal, Nishit P. Parikh, Debaprosad Dutt, Chi-Yuan Lo:
A data model and architecture for VLSI/CAD databases. 276-279 - Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton:
SLIP: a software environment for system level interactive partitioning. 280-283 - Ernst Siepmann:
A data management interface as part of the framework of an integrated VLSI-design system. 284-287 - Richard J. Bonneau:
DEC's engineering to manufacturing BRIDGE system based on the D-BUS architecture. 288-291 - Srinivas Devadas:
Optimal layout via Boolean satisfiability. 294-297 - Yen-Chuen A. Wei, Chung-Kuan Cheng:
Towards efficient hierarchical designs by ratio cut partitioning. 298-301 - Jason Cong:
Pin assignment with global routing. 302-305 - Glenn Colón-Bonet, Eric M. Schwarz, D. G. Bostick, Gary D. Hachtel, Michael R. Lightner:
On optimal extraction of combinational logic and don't care sets from hardware description languages. 308-311 - Seiyang Yang, Maciej J. Ciesielski:
PLA decomposition with generalized decoders. 312-315 - Robert K. Brayton, Fabio Somenzi:
An exact minimizer for Boolean relations. 316-319 - Carl Ebeling, Zhanbing Wu:
WireLisp: combining graphics and procedures in a circuit specification language. 322-325 - Larry G. Jones:
Fast incremental netlist compilation of hierarchical schematics. 326-329 - Tsung D. Lee, Lawrence P. McNamee:
Structure optimization in logic schematic generation. 330-333 - Jan Madsen
A new approach to optimal cell synthesis. 336-339 - Antun Domic, Samuel Levitin, Nathan Phillips, Channeary Thai, Thomas R. Shiple, Dilip Bhavsar, Clint Bissel:
CLEO: a CMOS layout generator. 340-343 - Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An optimal transistor-chaining algorithm for CMOS cell layout. 344-347 - P. K. Sun:
CETUS-a versatile custom cell synthesizer. 348-351 - Kwang-Ting Cheng, Vishwani D. Agrawal:
Design of sequential machines for efficient test generation. 358-361 - Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Test generation for highly sequential circuits. 362-365 - Thirumalai Sridhar:
FACT-a testability analysis methodology. 366-369 - Paul J. Rankin, J. M. Siemensma:
Analogue circuit optimization in a graphical environment. 372-375 - John S. Wenstrand, Hiroshi Iwai, Robert W. Dutton:
A manufacturing-oriented environment for synthesis of fabrication processes. 376-379 - Allen M. Dewey, Stephen W. Director:
Yoda: a framework for the conceptual design VLSI systems. 380-383 - Hamideh Afsarmanesh, Esther Brotoatmodjo, Kwang June Byeon, Alice C. Parker:
The EVE VLSI information management environment. 384-387 - Massoud Pedram, Bryan Preas:
Interconnection length estimation for optimized standard cell layouts. 390-393 - David P. LaPotin, Y.-H. Chen:
Early matching of system requirements and package capabilities. 394-397 - Parameswaran Ramanathan, Kang G. Shin:
A clock distribution scheme for nonsymmetric VLSI circuits. 398-401 - Donald J. Erdman, Donald J. Rose:
A Newton waveform relaxation algorithm for circuit simulation. 404-407 - Richard Burch, Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang, Paul F. Cox:
PGS and PLUCGS-two new matrix solution techniques for general circuit simulation. 408-411 - Mark W. Reichelt, Jacob K. White, Jonathan Allen:
Waveform relaxation for transient simulation of two-dimensional MOS devices. 412-415 - Kaushik Roy, Jacob A. Abraham, Kaushik De, Stephen L. Lusky:
Synthesis of delay fault testable combinational logic. 418-421 - Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison:
On properties of algebraic transformation and the multifault testability of multilevel logic. 422-425 - Patrick C. McGeer, Robert K. Brayton:
Consistency and observability invariance in multi-level logic synthesis. 426-429 - Hee Yong Youn, Adit D. Singh:
An efficient channel routing algorithm for defective arrays. 432-435 - Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Routing using a pyramid data structure. 436-439 - Raja Venkateswaran, Pinaki Mazumder:
HAM-a hardware accelerator for multi-layer wire routing. 440-443 - Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild:
FDT-a design tool for switched capacitor filters. 446-449 - Masato Mogaki, Naoki Kato, Youko Chikami, Naoyuki Yamada, Yasuhiro Kobayashi:
LADIES: an automatic layout system for analog LSI's. 450-453 - C. Leonard Berman, Louise Trevillyan:
Functional comparison of logic designs for VLSI circuits. 456-459 - Asher Wilk, Amir Pnueli:
Specification and verification of VLSI systems. 460-463 - Miron Abramovici, David T. Miller, Rabindra K. Roy:
Dynamic redundancy identification in automatic test generation. 466-469 - Hyoung B. Min, William A. Rogers, Hwei-Tsu Ann Luh:
FANHAT: fanout oriented hierarchical automatic test generation system. 470-473 - Yoshihiro Kitamura:
Exact critical path tracing fault simulation on massively parallel processor AAP2. 474-477 - Manfred Geilert:
High-speed compiled-code simulation of transition faults. 478-481 - D. F. Wong
An algorithm for hierarchical floorplan design. 484-487 - Sai-keung Dong, Jason Cong, C. L. Liu:
Constrained floorplan design for flexible blocks. 488-491 - Wing K. Luk, Alvar A. Dean, John W. Mathews:
Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout. 492-495 - David M. Lewis:
Hierarchical compiled event-driven logic simulation. 498-501 - Mary L. Bailey, Lawrence Snyder:
A model for comparing synchronization strategies for parallel logic-level simulation. 502-505 - Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
Portable parallel logic and fault simulation. 506-509 - Peter R. O'Brien, Thomas L. Savarino:
Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation. 512-515 - Cheryl Harkness, Daniel P. Lopresti:
Modeling uncertainty in RC timing analysis. 516-519 - Habib Youssef, Eugene Shragowitz, Lionel Bening:
Critical path issue in VLSI design. 520-523 - Krishna P. Belkhale, Prithviraj Banerjee:
PACE2: an improved parallel VLSI extractor with parameter extraction. 526-529 - James Janak, David D. Ling, Hao-Ming Huang:
C3DSTAR: a 3D wiring capacitance calculator. 530-533 - Jean-Claude Dufourd:
The Stickizer: a layout to symbolic converter. 534-537 - José Pineda de Gyvez, Jochen A. G. Jess:
A layout defect-sensitivity extractor. 538-541 - Hamid Savoj, Abdul A. Malik, Robert K. Brayton:
Fast two-level logic minimizers for multi-level logic synthesis. 544-547 - Reily M. Jacoby, P. Moceyunas, Hyunwoo Cho, Gary D. Hachtel:
New ATPG techniques for logic optimization. 548-551 - Kuang-Chien Chen, Saburo Muroga:
SYLON-DREAM: a multi-level network synthesizer. 552-555 - Yusuke Matsunaga, Masahiro Fujita:
Multi-level logic optimization using binary decision diagrams. 556-559 - Magdy S. Abadir:
TIGER: testability insertion guidance expert system. 562-565 - Yi-Nan Shen, Fabrizio Lombardi:
Fault detection in a testable PLA with low overhead for production testing. 566-569 - Nirmal R. Saxena, Edward J. McCluskey:
Arithmetic and galois checksums. 570-573 - Robert C. Aitken, Vinod K. Agarwal:
A diagnosis method using pseudo-random vectors without intermediate signatures. 574-577
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