default search action
DFT 1993: Venice, Italy
- Fabrizio Lombardi, Mariagiovanna Sami, Yvon Savaria, Renato Stefanelli:
The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings. IEEE Computer Society 1993, ISBN 0-8186-3502-9
Fault Tolerant Architectures
- A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson:
System Level Policies for Fault Tolerance Issues in the FERMI Project. DFT 1993: 1-8 - Raphaël Rochet, Régis Leveugle, Gabriele Saucier:
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT 1993: 9-16
Fault Tolerant Structures
- Liangkung Lin, G. Robert Redinbo:
Block Implementation of Fault-Tolerant LMS Adaptive FIR Filters. DFT 1993: 17-24 - Hee Yong Youn, Kyung Ook Lee:
Fault-Tolerant Sorting Using VLSI Processor Arrays. DFT 1993: 25-32 - Gian Carlo Cardarilli, M. Di Zenzo, Pat O. Pistilli, Adelio Salsano:
A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks. DFT 1993: 33-40 - Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey:
High Level Synthesis Techniques for Efficient Built-In-Self Repair. DFT 1993: 41-48 - Hannu H. Kari, Heikki Saikkonen, Fabrizio Lombardi:
Detection of Defective Media in Disks. DFT 1993: 49-55
Reconfiguration
- Hussain Al-Asaad, Elias S. Manolakos:
A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. DFT 1993: 56-63 - Chor Ping Low, Hon Wai Leong:
On the Reconfiguration of Degradable VLSI/WSI Arrays. DFT 1993: 64-71 - Chouki Aktouf, Chantal Robach, Guy Mazaré, J. Johansson:
Functional Testing and Reconfiguration of MIMD Machines. DFT 1993: 72-79 - Hideo Ito:
A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. DFT 1993: 80-87 - José Salinas, Fabrizio Lombardi:
On the Reconfigurable Operation of Arrays with Defects for Image Processing. DFT 1993: 88-95
Physical Analysis
- A. Kerek:
Front-end Electronics in the Radiation Environment of LHC. DFT 1993: 96-100 - Víctor H. Champac, Antonio Rubio, Joan Figueras:
Analysis of the Floating Gate Defect in CMOS. DFT 1993: 101-108 - A. P. Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. DFT 1993: 109-116 - Hua Xue, Chennian Di, Jochen A. G. Jess:
Fast Multi-Layer Critical Area Computation. DFT 1993: 117-124
Yield Modeling
- Enrico Ferrati, Magneti Marelli:
TEh Reliability of the Integrated Circuits in Automotive Industry. DFT 1993: 125-126 - Randall S. Collica:
A Logistic Regression Yield Model for SRAM Bit Fail Patterns. DFT 1993: 127-135 - Charles H. Stapper, J. A. Patrick, R. J. Rosner:
Yield Model for ASIC and Processor Chips. DFT 1993: 136-143 - J. Crépeau, Claude Thibeault, Yvon Savaria:
Some Results on Yield and Local Design Rule Relaxation. DFT 1993: 144-151 - Frederic Duvivier, M. Rivier, B. Burtschy, J. J. Charlot:
Use of a Segmentation Technique to Analyze the Variability of the Yield of a Mature CMOS SRAM. DFT 1993: 152-158
Design for Yield
- Zahava Koren, Israel Koren:
Does the Floorplan of a Chip Affect Its Yield? DFT 1993: 159-166 - Israel A. Wagner, Israel Koren:
An Interactive Yield Estimator as a VLSI CAD Tool. DFT 1993: 167-174 - Venkat K. R. Chiluvuri, Israel Koren:
Topological Optimization of PLAs for Yield Enhancement. DFT 1993: 175-182 - Eiji Fujiwara, Masaharu Tanaka:
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. DFT 1993: 183-190
Testing Techniques
- Giacomo Buonanno, Franco Fummi, Donatella Sciuto:
Fault Detection in Sequential Circuits through Functional Testing. DFT 1993: 191-198 - M. Rullán, F. C. Blom, Joan Oliver, Carles Ferrer:
Layout Level Design for Testability Strategy Applied to a CMOS Cell Library. DFT 1993: 199-206 - Michel Renovell, Joan Figueras:
Current Testing Viability in Dynamic CMOS Circuits. DFT 1993: 207-214 - David Wessels, Jon C. Muzio:
Probabilistic Identification of Critical Components for Circuit Delays. DFT 1993: 215-222 - Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza:
Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. DFT 1993: 223-230
Testable Architectures
- Graham Frearson:
The T9000 Transputer: A Practical Example of the Application of Standard Test Techniques. DFT 1993: 231-238 - Egor S. Sogomonyan, Michael Gössel:
Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection. DFT 1993: 239-246 - Xiaoling Sun, Micaela Serra:
Design and Implementation of a Merged On-Line and Off-Line Self Textable Architecture. DFT 1993: 247-254 - Dah-Yea Wei, Jung Hwan Kim, T. R. N. Rao:
Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays. DFT 1993: 255-262
Self-Checking and Error-Correcting Architectures
- Jien-Chung Lo, Eiji Fujiwara:
A Probabilistic Measurement for Totally Self-Checking Circuits. DFT 1993: 263-270 - Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. DFT 1993: 271-278 - Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
A Highly Testable 1-out-of-3 CMOS Checker. DFT 1993: 279-286 - Yuang-Ming Hsu, Earl E. Swartzlander Jr.:
VLSI Concurrent Error Correcting Adders and Multipliers. DFT 1993: 287-294
Defect/Fault Tolerance in Analog Systems
- D. Taylor, P. S. A. Evans, D. Marland:
Functional Testing of Linear Circuits Using Transient Response Analysis. DFT 1993: 295-302 - Alessandra Fanni, Alessandro Giua, Enrico Sandoli:
Neural Networks for Multiple Fault Diagnosis in Analog Circuits. DFT 1993: 303-310 - P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Realistic Fault Analysis of CMOS Analog Building Blocks. DFT 1993: 311-318 - Manoj Sachdev:
Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. DFT 1993: 319-326 - Nagendra Kumar, Philippe O. Pouliquen, Andreas G. Andreou:
Device Mismatch Limitations on the Performance of a Hamming Distance Classifier. DFT 1993: 327-334
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: