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10th Asia-Pacific Computer Systems Architecture Conference 2005: Singapore
- Thambipillai Srikanthan
, Jingling Xue, Chip-Hong Chang:
Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings. Lecture Notes in Computer Science 3740, Springer 2005, ISBN 3-540-29643-3
Keynote Address I
- Ruby B. Lee:
Processor Architecture for Trustworthy Computers. 1-2
Energy Efficient and Power Aware Techniques
- Amjad Mohsen, Richard Hofmann:
Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems. 3-14 - Juan L. Aragón, Alexander V. Veidenbaum:
Energy-Effective Instruction Fetch Unit for Wide Issue Processors. 15-27 - Shu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkumar:
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty. 28-40 - Cheol Kim, Sung Chung, Chu Shik Jhon:
An Innovative Instruction Cache for Embedded Processors. 41-51 - David Fitrio, Jugdutt Singh, Aleksandar Stojcevski:
Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor. 52-64
Methodologies and Architectures for Application-Specific Systems
- Ming Z. Zhang, Hau T. Ngo, Vijayan K. Asari:
Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution. 65-78 - Su-Jin Lee, Cheong-Ghil Kim, Shin-Dug Kim:
A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC. 79-89 - Siti Yuhaniz, Tanya Vladimirova, Martin Sweeting:
Embedded Intelligent Imaging On-Board Small Satellites. 90-103 - Jongmyon Kim, D. Scott Wills, Linda M. Wills:
Architectural Enhancements for Color Image and Video Processing on Embedded Systems. 104-117 - Yufeng Zhang, Yi Zhou, Jianhua Chen, Xinling Shi, Zhenyu Guo:
A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output. 118-130
Processor Architectures and Microarchitectures
- Lei Yang, Morteza Biglari-Abhari, Zoran A. Salcic:
A Power-Efficient Processor Core for Reactive Embedded Applications. 131-142 - Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang:
A Stream Architecture Supporting Multiple Stream Execution Models. 143-156 - Kostas Bousias, Chris R. Jesshope:
The Challenges of Massive On-Chip Concurrency. 157-170 - Jih-Ching Chiu, Ren-Bang Lin:
FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit. 171-185
High-Reliability and Fault-Tolerant Architectures
- Sheng-Kai Hung, Yarsun Hsu:
Modularized Redundant Parallel Virtual File System. 186-199 - Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras:
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. 200-214 - Xinhua Zhang, Peter Loh:
A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes. 215-228 - Sun-Yuan Hsieh:
Embedding of Cycles in the Faulty Hypercube. 229-235
Compiler and OS for Emerging Architectures
- Canqun Yang, Xuejun Yang, Jingling Xue:
Improving the Performance of GCC by Exploiting IA-64 Architectural Features. 236-251 - Pramod Ramarao, Akhilesh Tyagi:
An Integrated Partitioning and Scheduling Based Branch Decoupling. 252-268 - Feng Zhou, Junchao Zhang, Chengyong Wu, Zhaoqing Zhang:
A Register Allocation Framework for Banked Register Files with Access Constraints. 269-280 - Flavius Gruian
Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems. 281-294 - Chang Wu Yu
Irregular Redistribution Scheduling by Partitioning Messages. 295-309
Data Value Predictions
- Yong Xiao, Xingming Zhou, Kun Deng:
Making Power-Efficient Data Value Predictions. 310-322 - You-Jan Tsai, Jong-Jiann Shieh:
Speculative Issue Logic. 323-335 - Veerle Desmet, Lieven Eeckhout, Koen De Bosschere:
Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction. 336-352 - Daniel R. Kelly, Braden J. Phillips:
Arithmetic Data Value Speculation. 353-366 - Xiao-Feng Li, Chen Yang, Zhao-Hui Du, Tin-Fook Ngai:
Exploiting Thread-Level Speculative Parallelism with Software Value Prediction. 367-388
Keynote Address II
- Jesse Fang:
Challenges and Opportunities on Multi-core Microprocessor. 389-390
Reconfigurable Computing Systems and Polymorphic Architectures
- K. S. Tham, Douglas L. Maskell:
Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures. 391-404 - Jiho Chang, JongSu Yi, JunSeong Kim:
A Switch Wrapper Design for SNA On-Chip-Network. 405-414 - Marco Torre, Usama Malik, Oliver Diessel:
A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs. 415-428 - Jacop Yanto, Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell:
Biological Sequence Analysis with Hidden Markov Models on an FPGA. 429-439 - P. C. Kwan, C. T. Clarke:
FPGAs for Improved Energy Efficiency in Processor Based Systems. 440-449 - Siew Kei Lam, Yun Deng, Thambipillai Srikanthan
Morphable Structures for Reconfigurable Instruction Set Processors. 450-463
Interconnect Networks and Network Interfaces
- Hankook Jang, Sang-Hwa Chung, Soo-Cheol Oh:
Implementation of a Hybrid TCP/IP Offload Engine Prototype. 464-477 - Hyeong-Ok Lee, Jong-Seok Kim, Kyoung-Wook Park, Jeonghyun Seo, Eunseuk Oh:
Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations. 478-487 - Fangai Liu, Xinhua Wang, Liancheng Xu:
The Channel Assignment Algorithm on RP(k) Networks. 488-498 - Tingrong Lu, Chengcheng Sui, Yushu Ma, Jinsong Zhao, Yongtian Yang:
Extending Address Space of IP Networks with Hierarchical Addressing. 499-508 - Navid Imani, Hamid Sarbazi-Azad:
The Star-Pyramid Graph: An Attractive Alternative to the Pyramid. 509-519 - Huaxi Gu
Building a Terabit Router with XD Networks. 520-528
Parallel Architectures and Computation Models
- Suresh Sundaram, V. Mani, S. N. Omkar, Hyoung Joong Kim:
A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time. 529-539 - Zhen Liu, Jiaoying Shi, Haoyu Peng, Hua Xiong:
D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters. 540-550 - Jongmyon Kim, D. Scott Wills, Linda M. Wills:
Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures. 551-565 - Kyong Jung, Chanik Park:
A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling. 566-579
Hardware-Software Partitioning, Verification, and Testing of Complex Architectures
- Wu Jigang, Thambipillai Srikanthan
Minimizing Power in Hardware/Software Partitioning. 580-588 - Youhui Zhang, Liu Dong, Yu Gu, Dongsheng Wang:
Exploring Design Space Using Transaction Level Models. 589-599 - DongSup Song, Sungho Kang:
Increasing Embedding Probabilities of RPRPs in RIN Based BIST. 600-613 - Jin-Ho Ahn, Byung In Moon, Sungho Kang:
A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture. 614-624
Architectures for Secured Computing
- T. S. B. Sudarshan, Rahil Mir, S. Vijayalakshmi:
DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques. 625-639 - Khaled Z. Ibrahim:
Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor. 640-654 - Dan Mossop, Ronald Pose:
Covert Channel Analysis of the Password-Capability System. 655-668
Simulation and Performance Evaluation
- Andy Georges
Comparing Low-Level Behavior of SPEC CPU and Java Workloads. 669-679 - Jong-Sun Kim, Ji-Yoon Yoo:
Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control. 680-692 - Ravi Kumar Satzoda, Chip-Hong Chang
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. 693-706
Architectures for Emerging Technologies and Applications I
- Yunbo Wu, Zhishu Li, Yunhai Wu, Zhihua Chen, Tun Lu, Li Wang, Jianjun Hu:
Analysis of Real-Time Communication System with Queuing Priority. 707-713 - Sai Gopalan, Gayathri Venkataraman, Sabu Emmanuel:
FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks. 714-727 - Sun-Kuk Noh:
A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems. 728-735
Memory Systems Hierarchy and Management
- Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung
Cache Leakage Management for Multi-programming Workloads. 736-749 - Hou Rui, Fuxin Zhang, Weiwu Hu:
A Memory Bandwidth Effective Cache Store Miss Policy. 750-760 - Mehdi Modarressi, Maziar Goudarzi
Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance. 761-774 - Weng-Fai Wong
Targeted Data Prefetching. 775-786
Architectures for Emerging Technologies and Applications II
- Pramod Kumar Meher:
Area-Time Efficient Systolic Architecture for the DCT. 787-794 - Gab Jung, Seong Park, Jung Kim:
Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform. 795-804 - Himanshu Thapliyal
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. 805-817 - In-Su Yoon, Sang-Hwa Chung:
Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System. 818-830
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