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CICC 2011: San Jose, California, USA
- Rakesh Patel, Tom Andre, Aurangzeb Khan:
2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011. IEEE 2011, ISBN 978-1-4577-0222-8 - Hajir Hedayati, Mohamed Mobarak, Guillaume Varin, Philippe Meunier, Patrice Gamand, Edgar Sánchez-Sinencio, Kamran Entesari:
A fully integrated highly linear efficient power amplifier in 0.25µm BiCMOS technology for wireless applications. 1-4 - Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka:
A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller. 1-4 - Ranjit Gharpurey:
Managing linearity in radio front-ends. 1-8 - Yanjie Wang, Hua Wang, Christopher D. Hull, Shmuel Ravid:
A transformer-based broadband I/O matching-balun-T/R switch front-end combo scheme in standard CMOS. 1-4 - Muhammad Adnan, Ehsan Afshari:
A low conversion loss passive frequency doubler. 1-4 - Le Wang, Luke Theogarajan:
An 18µW 79dB-DR 20KHz-BW MASH ΔΣ modulator utilizing self-biased amplifiers for biomedical applications. 1-4 - Ramin Zanbaghi, Saurabh Saxena
, Gabor C. Temes, Terri S. Fiez:
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. 1-4 - Kentaro Yamamoto, Anthony Chan Carusone
A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs. 1-4 - Sanghyeon Lee, Jeongseok Chae
A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. 1-4 - Samira Zali Asl, Saurabh Saxena
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. 1-4 - Vikas Singh, Nagendra Krishnapura
A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. 1-4 - Ahmed Ashry, Hassan Aboushady
A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΔΣ ADC with a FoM of 1pJ/bit in 130nm CMOS. 1-4 - Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. 1-4 - Paul Merolla, John V. Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra S. Modha:
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm. 1-4 - Y. William Li, Hasnain Lakdawala:
Smart integrated temperature sensor - mixed-signal circuits and systems in 32-nm and beyond. 1-8 - Wei-Kai Chan, Yu-Hsiang Tseng, Pei-Kuei Tsung, Tzu-Der Chuang, Yi-Min Tsai, Wei-Yin Chen, Liang-Gee Chen
ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor. 1-4 - Erik Ryman, Anders Emrich, Stefan Back Andersson, J. Riesbeck, Lars J. Svensson, Per Larsson-Edefors:
3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry. 1-4 - Tom Malzbender:
Understanding the Antikythera Mechanism. 1 - Ali Hajimiri
Timing inaccuracy of clocks. 1 - Harmeet Bhugra:
Frequency reference challenges - a systemic view. 1 - Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini
A dither-less all digital PLL for cellular transmitters. 1-8 - Wu-Hsin Chen, Wing-Fai Loke, Gabriel J. Thompson, Byunghoo Jung:
A 0.5-V, 440-µW frequency synthesizer for implantable medical devices. 1-4 - Ja-Yol Lee, Mi-Jeong Park, Byonghoon Mhin, Seongdo Kim, Moon-Yang Park, Hyunku Yu:
A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation. 1-4 - Mohammad Hekmat, David K. Su, Bruce A. Wooley:
A quadrature LO generator using bidirectionally-coupled oscillators for 60-GHz applications. 1-4 - Feng Zhao, Fa Foster Dai:
A 0.6V quadrature VCO with optimized capacitive coupling for phase noise reduction. 1-4 - Shen Wang, Dong Sam Ha, Beomsup Kim, Vipul Chawla:
A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation. 1-4 - Chun-Wei Hsu, Karthik Tripurari, Shih-An Yu, Peter R. Kinget
A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression. 1-4 - Pyoungwon Park, Dongmin Park, SeongHwan Cho:
A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL. 1-4 - Jianlei Shi, Brian P. Otis:
A sub-100µW 2GHz differential colpitts CMOS/FBAR VCO. 1-4 - Sherif Galal, Hui Zheng, Khaled Abdelfattah, Vinay Chandrasekhar, Iuri Mehr, Alex Jianzhong Chen, John Platenak, Nir Matalon, Todd Brooks:
A 60mW 1.15mA/channel Class-G Stereo Headphone Driver with 111dB DR and 120dB PSRR. 1-4 - Lingkai Kong, Yue Lu, Elad Alon:
A multi-GHz area-efficient comparator with dynamic offset cancellation. 1-4 - Nasrin Jaffari, Katelijn Vleugels, Bruce A. Wooley:
Zero-pole modulation and demodulation for noise reduction in charge amplifiers. 1-4 - Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi:
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. 1-7 - Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara:
Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. 1-4 - Mohamed H. Abu-Rahma, Ying Chen, Wing Sy, Wee Ling Ong, Leon Yeow Ting, Sei Seung Yoon, Michael Han, Esin Terzioglu:
Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS. 1-4 - Christophe Muller
Design challenges for prototypical and emerging memory concepts relying on resistance switching. 1-7 - Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Kazuyoshi Okamoto, Kazutaka Mori, Kazumasa Yanagisawa:
A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias. 1-4 - Srivatsan Chellappa, Aritra Dey, Lawrence T. Clark:
Improved circuits for microchip identification using SRAM mismatch. 1-4 - John R. Long, Yi Zhao, Y. Jin, Wanghua Wu, Marco Spirito
Circuit technologies for mm-wave wireless systems on silicon. 1-8 - Kun-Hin To, Vishal P. Trivedi:
A 76-81GHz transmitter with 10dBm output power at 125 °C for automotive radar in 65nm bulk CMOS. 1-4 - Mehmet Parlak
A 2.9-dB noise figure, Q-band millimeter-wave CMOS SOI LNA. 1-4 - Omeed Momeni, Ehsan Afshari:
A high gain 107 GHz amplifier in 130 nm CMOS. 1-4 - Ozgur Inac, Andy Fung, Gabriel M. Rebeiz:
Double-balanced 130-180 GHz passive and balanced 145-165 GHz active mixers in 45 nm CMOS. 1-4 - Maryam Tabesh, Amin Arbabian, Ali M. Niknejad:
60GHz low-loss compact phase shifters using a transformer-based hybrid in 65nm CMOS. 1-4 - Tsung-Che Lu, Lan-Da Van, Chi-Sheng Lin, Chun-Ming Huang:
A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications. 1-4 - Ho-Young Lee, David Gubbins, Bumha Lee, Un-Ku Moon:
A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC. 1-4 - Jack Chu, Hae-Seung Lee:
A 450 MS/s 10-bit time-interleaved zero-crossing based ADC. 1-4 - I-Ning Ku, Zhiwei Xu, Yen-Cheng Kuan
A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS. 1-4 - Trent McConaghy:
High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper). 1-8 - Myeong-Jae Park, Hanseok Kim, Minbok Lee, Jaeha Kim:
Fast and accurate event-driven simulation of mixed-signal systems with data supplementation. 1-4 - Yu Bi, Simon de Graaf, Nick van der Meijs:
Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique. 1-4 - Yasumichi Takai, Masanori Hashimoto
Power gating implementation for noise mitigation with body-tied triple-well structure. 1-4 - Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar
Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. 1-4 - Ru Huang, Runsheng Wang, Jing Zhuge, Changze Liu, Tao Yu, Liangliang Zhang, Xin Huang, Yujie Ai, Jinbin Zou, Yuchao Liu, Jiewen Fan, Huailin Liao, Yangyuan Wang:
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling. 1-8 - Yousef Shakhsheer, Sudhanshu Khanna, Kyle Craig, Saad Arrabi, John C. Lach, Benton H. Calhoun:
A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V. 1-4 - Noah Sturcken, Michele Petracca, Steve B. Warren, Luca P. Carloni
An integrated four-phase buck converter delivering 1A/mm2 with 700ps controller delay and network-on-chip load in 45-nm SOI. 1-4 - Justin Shi, Ying-Chih Hsu, Eric G. Soenen, Alan Roth, Justin Gaither:
A wide-range DC/DC converter with 2nd order digital compensation and direct battery connection in 40nm CMOS. 1-4 - Xiaohan Gong, Jinhua Ni, Zhiliang Hong, Bill Liu:
An 80% peak efficiency, 0.84mW sleep power consumption, fully-integrated DC-DC converter with buck/LDO mode control. 1-4 - Jen-Chieh Tsai, Chi-Lin Chen, Yi-Ting Chen, Chia-Lung Ni, Chun-Yen Chen, Ke-Horng Chen
Perturbation on-time (POT) control and inhibit time control (ITC) in suppression of THD of power factor correction (PFC) design. 1-4 - Xiwen Zhang, Hoi Lee:
A reconfigurable 2× / 2.5× / 3× / 4× SC DC-DC regulator for enhancing area and power efficiencies in transcutaneous power transmission. 1-4 - Yu-Huei Lee, Ming-Yan Fan, Wei-Chung Chen, Ke-Horng Chen
A near-zero cross-regulation single-inductor bipolar-output (SIBO) converter with an active-energy-correlation control for driving cholesteric-LCD. 1-4 - Yang Tang, Zuochang Ye, Yan Wang:
Broadband compact model for on-chip mm-wave transformers and baluns with emphasis on capacitive coupling effects. 1-4 - N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
Bottom-up digital system-level reliability modeling. 1-4 - Bart A. De Vries, Andries J. Scholten
Wafer-specific centering of compact transistor model parameters for advanced technologies and models. 1-4 - Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei:
Area efficient phase calibration of a 1.6 GHz multiphase DLL. 1-4 - Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu:
Digital clock and data recovery circuit design: Challenges and tradeoffs. 1-8 - Youngmin Park, David D. Wentzloff:
An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS. 1-4 - Xiaochen Yang, Jin Liu:
An open-loop 10GHz 8-phase clock generator in 65nm CMOS. 1-4 - Jan Craninckx
SAW-less software-defined radio transceivers in 40nm CMOS. 1-8 - Nan Qi, Yang Xu, Baoyong Chi, Yang Xu, Xiaobao Yu, Xing Zhang, Zhihua Wang:
A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS. 1-4 - Ralph Mason, Justin Fortier, Chris DeVries:
Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking. 1-4 - Jae Hyuk Jang, David F. Berdy, Jangjoon Lee, Dimitrios Peroulis
A wireless sensor node for condition monitoring powered by a vibration energy harvester. 1-4 - Michael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes:
Design and technology interaction beyond 32nm. 1-9 - Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya:
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs. 1-4 - S. H. Yang, J. Y. Sheu, M. K. Ieong, M. H. Chiang, T. Yamamoto, J. J. Liaw, S. S. Chang, Y. M. Lin, T. L. Hsu, J. R. Hwang, J. K. Ting, C. H. Wu, K. C. Ting, F. C. Yang, C. M. Liu, I. L. Wu, Y. M. Chen, S. J. Chent, K. S. Chen, J. Y. Cheng, M. H. Tsai, W. Chang, R. Chen, C. C. Chen, T. L. Lee, C. K. Lin, S. C. Yang, Y. M. Sheu, J. T. Tzeng, L. C. Lu, S. M. Jang, Carlos H. Diaz
28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications. 1-5 - Subramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.:
Three Dimensional integration - Considerations for memory applications. 1-7 - Dragomir Milojevic
DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. 1-4 - William R. Bottoms:
Test challenges for 3D integration (an invited paper for CICC 2011). 1-8 - Nicholas Olson, Nathan Jack, Vrashank Shukla, Elyse Rosenbaum:
CDM-ESD induced damage in components using stacked-die packaging. 1-4 - Alan Rolf Mickelson:
Silicon photonics for on-chip interconnections. 1-8 - Siavash Fallahi, Delong Cui, Deyi Pi, Rose Zhu, Greg Unruh, Marcel Lugthart, Afshin Momtaz:
A 19 mW/lane Serdes transceiver for SFI-5.1 application. 1-4 - Yunzhi Dong, Kenneth W. Martin:
A monolithic 3.125 Gbps fiber optic receiver front-end for POF applications in 65 nm CMOS. 1-4 - Michael Georgas, Jonathan C. Leu, Benjamin Moss, Chen Sun, Vladimir Stojanovic:
Addressing link-level design tradeoffs for integrated photonic interconnects. 1-8 - Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim:
A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS. 1-4 - Kangmin Hu, Tao Jiang, Samuel Palermo, Patrick Yin Chiang:
Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS. 1-4 - Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli:
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology. 1-4 - John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen:
Power-efficient I/O design considerations for high-bandwidth applications. 1-8 - Caspar P. L. van Vroonhoven, Kofi A. A. Makinwa:
Thermal diffusivity sensing: A new temperature sensing paradigm. 1-6 - Ayman ElSayed, Ahmed Elshennawy, Ahmed Elmallah, Ahmad Shaban
A self-clocked ASIC interface for MEMS gyroscope with 1m°/s/√Hz noise floor. 1-4 - Kiseok Song, Joonsung Bae, Long Yan, Hoi-Jun Yoo:
A 20 µW contact impedance sensor for wireless body-area-network transceiver. 1-4 - Ruslana Shulyzki, Karim Abdelhalim, Arezu Bagheri, Carlos M. Florez, Peter L. Carlen, Roman Genov:
256-site active neural probe and 64-channel responsive cortical stimulator. 1-4 - Raymond E. Barnett, Ganesh K. Balachandran:
Power management subsystem with bi-directional DC to DC converter for μ-power biomedical applications. 1-4 - Edward K. F. Lee:
A capacitor-based AC-DC step-up converter for biomedical implants. 1-4 - Hyung-Min Lee
Fully integrated power-efficient AC-to-DC converter design in inductively-powered biomedical applications. 1-8 - Jacob K. Rosenstein, Sebastian Sorgenfrei, Kenneth L. Shepard:
Noise and bandwidth performance of single-molecule biosensors. 1-7 - Tajana Rosing:
Energy efficient computing in large scale systems. 1 - Vivek De:
Energy efficient designs with wide dynamic range. 1 - John Wawrzynek:
Advances and challenges of computing with FPGAs. 1 - Philip K. T. Mok:
High-efficient DC-DC converter design. 1 - Ming-Feng Huang:
A discrete-time charge-domain filter with bandwidth calibration for LTE application. 1-4 - Shang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh, Ka-Yi Yeh, Chung-Chi Jim Li:
A new CMOS image sensor readout structure for 3D integrated imagers. 1-4 - Changhui Hu, Patrick Yin Chiang:
All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS. 1-4 - Mihai A. T. Sanduleanu
A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI. 1-4 - Jacob Postman, Patrick Chiang:
Energy-efficient transceiver circuits for short-range on-chip interconnects. 1-4 - Michitaka Yoshino, Mitsuhiro Iwaide, Daigo Kuniyoshi, Hajime Ohtani, Akira Yasuda, Jun-ichi Okamura:
A novel audio playback chip using digitally driven speaker architecture with 80%@-10dBFS power efficiency, 5.5W@3.3V supply and 100dB SNR. 1-4 - Sanjeev K. Maheshwari, Emerson S. Fang, Sanjeev K. Aggarwal:
32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL. 1-4 - Jing Guo, Jiageng Huang, George Jie Yuan, Jessica Ka-Yan Law, Chi-Kong Yeung, Mansun Chan
A 38.6nV/Hz0.5 -59.6dB THD dual-band micro-electrode array signal acquisition IC. 1-4 - Adil Koukab, Omid Talebi Amiri:
Analysis and modeling of on-chip power combiners and their losses in LINC transmitters. 1-4 - Tsung-Yen Tsai, Gordon W. Roberts:
Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus. 1-4 - Lei Feng, Ram Sadhwani, Yaron Peperovits, Christopher D. Hull, Jonathan Jensen:
Overlapped inductors and its application on a shared RF front-end in a MultiStandard IC. 1-4 - Jongmoon Kim, Seokoh Yun, Wonkab Oh, Minsu Kil, Sanghyun Cho:
A true single SoC for UHF mobile RFID reader. 1-4 - Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Li, Seung-Hyuk Kang, Xiaochun Zhu, Wenqing Wu:
A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. 1-4 - Philip M. Chopp, Anas A. Hamoui:
A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz. 1-4 - Derek Ho
CMOS field-modulated color sensor. 1-4 - Zhenfei Peng, Shanshan Yang, Yong Feng, Zhiliang Hong, Bill Liu:
An 80% peak efficiency, 410mW, single supply rail powered Class-I linear audio amplifier. 1-4 - James F. Buller, Jay Fletcher, Steven Meyers, Moises E. Robinson, Francisco Tamayo, Amit Prakash, Dru Cabler:
Band-gap circuit design challenges in high-performance 32-nm technology. 1-4 - Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag:
Low power and error resilient PN code acquisition filter via statistical error compensation. 1-4 - Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano:
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. 1-4 - Navin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany:
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface. 1-4 - Bo Zhao, Xiangyu Zhang, Shoushun Chen:
A CMOS image sensor with on-chip motion detection and object localization. 1-4 - Jian Xu, Xiaobo Wu, Menglian Zhao, Rui Fan, Hanqing Wang, Xiaofen Ma, Bill Liu:
Ultra low-FOM high-precision ΔΣ modulators with fully-clocked SO and zero static power quantizers. 1-4 - Sheng-Li Huang, Yo-Sheng Lin, Jen-How Lee:
A Low-Power and low-noise 21∼29 GHz ultra-wideband receiver front-end in 0.18 µm CMOS technology. 1-4 - James F. Buckwalter, Joohwa Kim, Xuezhe Zheng, Guoliang Li, Kannan Raj, Ashok V. Krishnamoorthy:
A fully-integrated optical duobinary transceiver in a 130nm SOI CMOS technology. 1-4 - Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif:
Electrically-driven retargeting for nanoscale layouts. 1-4 - Emmanuel Hardy
A partial tree vector quantizer dynamic element matching technique for audio Δ-Σ converters. 1-4 - Shinichi Kubota, Nobuo Sasaki, Mohiuddin Hafiz, Akihiro Toya, Takamaro Kikkawa:
5 Gbps BPSK CMOS transmitter with on-chip antenna using Gaussian monocycle pulses. 1-4 - Aritra Dey, David R. Allee:
Amorphous silicon current steering digital to analog converter. 1-4 - Joseph N. Y. Aziz, Ark-Chew Wong, Andrew Chen, Derek Tam:
A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applications. 1-4 - Bangda Yang, Brian Drost, Sachin Rao, Pavan Kumar Hanumolu:
A high-PSR LDO using a feedforward supply-noise cancellation technique. 1-4 - Jong-In Kim, Wan Kim
A time-domain latch interpolation technique for low power flash ADCs. 1-4 - Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. 1-4 - Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi
A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. 1-4 - Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj:
A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. 1-4 - Le Zheng, Kuanfu Chen, Wentai Liu:
A non-coherent versatile DPSK receiver for high channel-density neural prosthesis. 1-4 - David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong:
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. 1-4 - Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi
Indirect phase noise sensing for self-healing voltage controlled oscillators. 1-4 - Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen:
An at-speed self-testable technique for the high speed domino adder. 1-4 - Liyuan Liu, Dongmei Li, Yafei Ye, Liangdong Chen, Zhihua Wang:
A 95dB SNDR audio ΔΣ modulator in 65nm CMOS. 1-4 - Lei Zhang, Xiangqing He, Yan Wang, Zhiping Yu:
A fully integrated CMOS nanoscale biosensor microarray. 1-4 - Jianqin Qian, Chun Zhang, Liji Wu, Xijin Zhao, Dingguo Wei, Zhihao Jiang, Yuhui He:
A passive UHF tag for RFID-based train axle temperature measurement system. 1-4 - Bei Peng, Guanzhong Huang, Hao Li, Peiyuan Wan, Pingfen Lin:
A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS. 1-4 - Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi:
Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM. 1-4
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