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"A Probabilistic Power Estimation Method for Combinational Circuits Under ..."

George Theodoridis et al. (2001)

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DOI: 10.1155/2001/12026

access: open

type: Journal Article

metadata version: 2023-05-08

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  - https://dblp.org/rec/journals/vlsi/TheodoridisTSG01
George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis:
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. VLSI Design 12(1): 69-79 (2001)

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