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George Theodoridis
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- affiliation: University of Patras, Greece
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2020 – today
- 2023
- [c45]Aimilios Leftheriotis
, Aphrodite Tzomaka, Dimitrios Danopoulos, George Lentaris, George Theodoridis, Dimitrios Soudris
Evaluating Versal ACAP and conventional FPGA platforms for AI inference. MOCAST 2023: 1-6 - 2022
- [c44]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. VLSI-SoC 2022: 1-6 - [c43]Nikolaos Kefalas, George Theodoridis:
An FPGA implementation of the VESA Display Stream Compression decoder. VLSI-SoC 2022: 1-6 - 2020
- [c42]S. Moraitis, D. Seitanidis, George Theodoridis, Odysseas G. Koufopavlou:
Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers. VLSI-SOC 2020: 46-51
2010 – 2019
- 2019
- [j27]Nikolaos Kefalas, George Theodoridis:
Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard. Integr. 69: 85-97 (2019) - [c41]Nikolaos Kefalas, George Theodoridis:
Implementing VESA Display Stream Compression Encoder in FPGAs. PATMOS 2019: 35-40 - 2018
- [j26]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis
Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. ACM Trans. Design Autom. Electr. Syst. 23(2): 26:1-26:24 (2018) - [c40]Panayiotis Alefragis
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. ARC 2018: 700-711 - [c39]Nikolaos Kefalas, George Theodoridis:
A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard. TSP 2018: 1-7 - 2017
- [c38]Nikolaos Kefalas
High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard. PATMOS 2017: 1-8 - [c37]Andreas Emeretlis, T. Tsakoulis, George Theodoridis, Panayiotis Alefragis
Task graph mapping and scheduling on heterogeneous architectures under communication constraints. SAMOS 2017: 239-244 - 2016
- [j25]Harris E. Michail, George Athanasiou, Vasilios I. Kelefouras, George Theodoridis, Thanos Stouraitis
Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. J. Circuits Syst. Comput. 25(4): 1650032:1-1650032:26 (2016) - [j24]Harris E. Michail, Georgios Athanasiou, George Theodoridis, Andreas Gregoriades
Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures. Microprocess. Microsystems 45: 227-240 (2016) - [j23]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis
A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms. ACM Trans. Embed. Comput. Syst. 15(1): 19:1-19:28 (2016) - [c36]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis
A hybrid approach for mapping and scheduling on heterogeneous multicore systems. SAMOS 2016: 360-365 - 2015
- [j22]Nikolaos Kefalas
A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter. Integr. 49: 65-77 (2015) - [c35]Andreas Emeretlis, V. Kefelouras, George Theodoridis, Maki Nanou, Christina Tanya Politi
FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links. EUSIPCO 2015: 1581-1585 - [c34]Nikolaos Kefalas
A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter. ICCE-Berlin 2015: 273-276 - [c33]Maki Nanou, Andreas Emeretlis, Christina Tanya Politi
40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links. ICTON 2015: 1-4 - [c32]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis
Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. ISVLSI 2015: 119-124 - 2014
- [j21]Georgios Athanasiou
Optimising the SHA-512 cryptographic hash function on FPGAs. IET Comput. Digit. Tech. 8(2): 70-82 (2014) - [j20]Harris E. Michail, Georgios Athanasiou
On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. Integr. 47(4): 387-407 (2014) - [c31]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis
A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures. IPDPS Workshops 2014: 176-182 - [c30]Nikolaos Kefalas
An 8K-UHD capable 8-stage pipeline deblocking filter for H.264/AVC. ISCCSP 2014: 570-573 - [c29]Andreas Emeretlis, George Theodoridis:
FPGA Implementations for Volterra DFEs. Panhellenic Conference on Informatics 2014: 23:1-23:5 - [c28]Andreas Emeretlis, George Theodoridis, George-Othon Glentis
High-performance FPGA implementations of volterra DFEs for optical fiber systems. ReConFig 2014: 1-8 - 2013
- [j19]George Athanasiou
High-performance FPGA implementations of the cryptographic hash function JH. IET Comput. Digit. Tech. 7(1): 29-40 (2013) - [j18]George Athanasiou
A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. J. Circuits Syst. Comput. 22(6) (2013) - 2012
- [j17]Harris E. Michail, George Athanasiou
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC. ACM Trans. Reconfigurable Technol. Syst. 5(1): 2:1-2:28 (2012) - [c27]George Athanasiou, Chara I. Chalkou, D. Bardis, Harris E. Michail, George Theodoridis, Costas E. Goutis:
High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. SECRYPT 2012: 126-135 - [c26]Harris E. Michail, George Athanasiou, Andreas Gregoriades, George Theodoridis, Costas E. Goutis:
On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. SECRYPT 2012: 270-275 - 2010
- [c25]Nikolaos Kefalas
A high throughput pipelined architecture for H.264/AVC deblocking filter. ICECS 2010: 387-391
2000 – 2009
- 2009
- [j16]George Theodoridis, Nikolaos Vassiliadis, Spiridon Nikolaidis
An integer linear programming model for mapping applications on hybrid systems. IET Comput. Digit. Tech. 3(1): 33-42 (2009) - [j15]Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
An Application Development Framework for ARISE Reconfigurable Processors. ACM Trans. Reconfigurable Technol. Syst. 2(4): 24:1-24:30 (2009) - [j14]Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 221-233 (2009) - 2008
- [c24]Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
ARISE Machines: Extending Processors with Hybrid Accelerators. ARC 2008: 195-206 - 2007
- [j13]Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. Microprocess. Microsystems 31(1): 1-14 (2007) - [c23]Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
The ARISE Reconfigurable Instruction Set Extensions Framework. ICSAMOS 2007: 153-160 - [i1]Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. CoRR abs/0710.4844 (2007) - 2006
- [j12]Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris:
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. J. Low Power Electron. 2(3): 356-364 (2006) - [j11]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis:
A high-performance data path for synthesizing DSP kernels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1154-1162 (2006) - [j10]Athanasios Kakarountas
High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. J. Supercomput. 37(2): 179-195 (2006) - [c22]Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis:
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. ARC 2006: 217-229 - [c21]Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
An automated development framework for a RISC processor with reconfigurable instruction set extensions. IPDPS 2006 - 2005
- [j9]Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris
A method for partitioning applications in hybrid reconfigurable architectures. Des. Autom. Embed. Syst. 10(1): 27-47 (2005) - [j8]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis:
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. J. Circuits Syst. Comput. 14(4): 877-893 (2005) - [j7]Nikolaos D. Zervas, George Theodoridis, Dimitrios Soudris:
Behavioral-level event-driven power management for DECT digital receivers. Microelectron. J. 36(2): 163-172 (2005) - [c20]Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. IPDPS 2005 - [c19]Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris
A methodology for partitioning DSP applications in hybrid reconfigurable systems. ISCAS (2) 2005: 1206-1209 - 2004
- [j6]Athanasios Milidonis, Gregory Dimitroulakos, Michalis D. Galanis, Athanasios P. Kakarountas
A Framework for Data Partitioning for C++ Data-Intensive Applications. Des. Autom. Embed. Syst. 9(2): 101-121 (2004) - [c18]Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE 2004: 247-252 - [c17]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. FCCM 2004: 275-276 - [c16]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. FPGA 2004: 252 - [c15]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. FPL 2004: 868-873 - [c14]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis:
A high performance data-path to accelerate DSP kernels. ICECS 2004: 495-498 - [c13]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. PATMOS 2004: 652-661 - [c12]Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis:
A Novel Constant-Time Fault-Secure Binary Counter. PATMOS 2004: 742-749 - [c11]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis:
A Novel Data-Path for Accelerating DSP Kernels. SAMOS 2004: 363-372 - [c10]Athanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor:
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. SCOPES 2004: 122-136 - 2003
- [j5]Paris Kitsos
An efficient reconfigurable multiplier architecture for Galois field GF(2m). Microelectron. J. 34(10): 975-980 (2003) - [c9]Gregory Dimitroulakos, Athanasios Milidonis, Michalis D. Galanis, George Theodoridis, Costas E. Goutis, Francky Catthoor:
Power aware data type refinement on the HIPERLAN/2. ICECS 2003: 216-219 - [c8]Paris Kitsos
An reconfigurable multiplier in GF(2m) for elliptic curve cryptosystem. ICECS 2003: 699-702 - [c7]Athanasios P. Kakarountas
A novel high-speed counter with counting rate independent of the counter's length. ICECS 2003: 1164-1167 - 2002
- [j4]S. Theoharis, George Theodoridis, Dimitrios Soudris
A fast and accurate delay dependent method for switching estimation of large combinational circuits. J. Syst. Archit. 48(4-5): 113-124 (2002) - 2001
- [j3]George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis:
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. VLSI Design 12(1): 69-79 (2001) - [j2]George Theodoridis, S. Theoharis, Dimitrios Soudris
A Fast and Accurate Method of Power Estimation for Logic Level Networks. VLSI Design 12(2): 205-219 (2001) - 2000
- [c6]Dimitrios Soudris
Low power design of a multi-mode transceiver. ISCAS 2000: 721-724 - [c5]Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. PATMOS 2000: 47-55 - [c4]George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis:
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. PATMOS 2000: 76-87
1990 – 1999
- 1999
- [j1]George Theodoridis, Spyros Theoharis, Dimitrios Soudris
A New Method for Low Power Design of Two-Level Logic Circuits. VLSI Design 9(2): 147-157 (1999) - [c3]George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis:
An efficient probabilistic method for logic circuits using real delay gate model. ISCAS (1) 1999: 286-289 - 1996
- [c2]Dimitrios Soudris, George Theodoridis, S. Theoharis, Adonios Thanailakis:
Low-power design of array architectures. ICECS 1996: 120-123 - [c1]George Theodoridis, S. Theoharis, Dimitrios Soudris, Odysseas G. Koufopavlou, Costas E. Goutis:
A novel approach for reducing the switching activity in two-level logic circuits. ICECS 1996: 840-843
Coauthor Index
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