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"VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing."

Suntae Hwang, Rochit Rajsuman (1997)

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DOI: 10.1155/1997/59329

access: open

type: Journal Article

metadata version: 2022-11-05

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  - journals/vlsi/HwangR97
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  - https://dblp.org/rec/journals/vlsi/HwangR97
Suntae Hwang, Rochit Rajsuman:
VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing. VLSI Design 5(3): 299-311 (1997)

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