More Web Proxy on the site http://driver.im/

default search action

combined dblp search
author search
venue search
publication search

ask others

"90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access ..."

Anisha Ramesh, Si-Young Park, Paul R. Berger (2011)

> Home

Details and statistics

DOI: 10.1109/TCSI.2011.2123630

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/RameshPB11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/RameshPB11
Anisha Ramesh, Si-Young Park, Paul R. Berger:
90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(10): 2432-2445 (2011)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.