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"High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition ..."

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima (1985)

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DOI: 10.1109/TC.1985.1676634

access: closed

type: Journal Article

metadata version: 2020-12-29

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  dblp key:
  - journals/tc/TakagiYY85
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  persistent URL:
  - https://dblp.org/rec/journals/tc/TakagiYY85
Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima:
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Trans. Computers 34(9): 789-796 (1985)

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