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"Static Test Compaction for Full-Scan Circuits Based on Combinational Test ..."

Irith Pomeranz, Sudhakar M. Reddy (2004)

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DOI: 10.1109/TC.2004.118

access: closed

type: Journal Article

metadata version: 2017-05-20

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  - https://dblp.org/rec/journals/tc/PomeranzR04b
Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. IEEE Trans. Computers 53(12): 1569-1581 (2004)

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