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"Designing interconnection buses in VLSI and WSI for maximum yield and ..."

Israel Koren, Zahava Koren, Dhiraj K. Pradhan (1988)

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DOI: 10.1109/4.330

access: closed

type: Journal Article

metadata version: 2024-11-05

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Israel Koren, Zahava Koren, Dhiraj K. Pradhan:
Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay. IEEE J. Solid State Circuits 23(3): 859-866 (1988)

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