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"A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer ..."

Koichi Fujiwara et al. (2015)

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DOI: 10.1587/TRANSFUN.E98.A.1392

access: closed

type: Journal Article

metadata version: 2020-10-26

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  - https://dblp.org/rec/journals/ieicet/FujiwaraKAYT15
Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1392-1405 (2015)

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