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"Cache-emulated register file: An integrated on-chip memory architecture ..."

Naifeng Jing et al. (2016)

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DOI: 10.1109/MICRO.2016.7783717

access: closed

type: Conference or Workshop Paper

metadata version: 2022-05-31

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  - conf/micro/JingWFYJLL16
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  - https://dblp.org/rec/conf/micro/JingWFYJLL16
Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang:
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. MICRO 2016: 14:1-14:12

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