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"Statistical Gate Sizing for Yield Enhancement at Post Layout Level."

Narender Hanchate, Nagarajan Ranganathan (2007)

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DOI: 10.1109/ISVLSI.2007.92

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  - https://dblp.org/rec/conf/isvlsi/HanchateR07a
Narender Hanchate, Nagarajan Ranganathan:
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI 2007: 245-252

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