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"Hybrid Multi-tile Vector Systolic Architecture for Accelerating ..."

Jay Shah, Nanditha Rao (2024)

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DOI: 10.1109/ISCAS58744.2024.10558268

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-16

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Jay Shah, Nanditha Rao:
Hybrid Multi-tile Vector Systolic Architecture for Accelerating Convolution on FPGAs. ISCAS 2024: 1-5

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