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"Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip ..."

Jae Hong Roh et al. (2021)

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DOI: 10.1109/ISOCC53507.2021.9613860

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-06

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  dblp key:
  - conf/isocc/RohLLS21
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  - https://dblp.org/rec/conf/isocc/RohLLS21
Jae Hong Roh, Useok Lee, Yongje Lee, Myung Hoon Sunwoo:
Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder. ISOCC 2021: 19-20

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