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"Speed-area optimized FPGA implementation for Full Search Block Matching."

Santosh Ghosh, Avishek Saha (2007)

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DOI: 10.1109/ICCD.2007.4601874

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/iccd/GhoshS07
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  persistent URL:
  - https://dblp.org/rec/conf/iccd/GhoshS07
Santosh Ghosh, Avishek Saha:
Speed-area optimized FPGA implementation for Full Search Block Matching. ICCD 2007: 13-18

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