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"Waiting false path analysis of sequential logic circuits for performance ..."

Kazuhiro Nakamura et al. (1998)

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DOI: 10.1145/288548.289059

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/iccad/NakamuraTKW98
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  - https://dblp.org/rec/conf/iccad/NakamuraTKW98
Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe:
Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD 1998: 392-395

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