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"Gate level representation of ECL circuits for fault modeling."

Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya (1991)

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DOI: 10.1109/GLSV.1991.143989

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya:
Gate level representation of ECL circuits for fault modeling. Great Lakes Symposium on VLSI 1991: 330-331

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