More Web Proxy on the site http://driver.im/

default search action

combined dblp search
author search
venue search
publication search

ask others

"Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class ..."

Kazuhiko Terada et al. (2012)

> Home

Details and statistics

DOI: 10.1109/FPL.2012.6339229

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/TeradaUISTU12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/TeradaUISTU12
Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano:
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. FPL 2012: 639-642

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.