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"Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level ..."

Steve Dai et al. (2017)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2017-02-03

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  - electronic edition @ acm.org
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  dblp key:
  - conf/fpga/DaiZLSGBZ17
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  persistent URL:
  - https://dblp.org/rec/conf/fpga/DaiZLSGBZ17
Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang:
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. FPGA 2017: 189-194

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