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"A DSP ASIC design flow based on VHDL and ASIC-emulation."

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Jan Andersson (1995)

Dagstuhl

Trier

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DOI: 10.1109/EURDAC.1995.527460

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jan Andersson:
A DSP ASIC design flow based on VHDL and ASIC-emulation. EURO-DAC 1995: 562-567

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