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"Efficient DPA-Resistance Verification Method with Smaller Number of Power ..."

Hiroki Ito et al. (2012)

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DOI: 10.1109/DSD.2012.46

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/dsd/ItoSHF12
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  persistent URL:
  - https://dblp.org/rec/conf/dsd/ItoSHF12
Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino:
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. DSD 2012: 735-738

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