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"BCDL: A high speed balanced DPL for FPGA with global precharge and no ..."

Maxime Nassar et al. (2010)

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DOI: 10.1109/DATE.2010.5456932

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  dblp key:
  - conf/date/NassarBDDG10
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  persistent URL:
  - https://dblp.org/rec/conf/date/NassarBDDG10
Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley:
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE 2010: 849-854

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