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Maxime Nassar
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2010 – 2019
- 2012
- [c12]Youssef Souissi, Shivam Bhasin, Sylvain Guilley, Maxime Nassar, Jean-Luc Danger:
Towards Different Flavors of Combined Side Channel Attacks. CT-RSA 2012: 245-259 - [c11]Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger:
RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. DATE 2012: 1173-1178 - 2011
- [c10]Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar:
Embedded systems security: An evaluation methodology against Side Channel Attacks. DASIP 2011: 230-237 - [c9]Maxime Nassar, Sylvain Guilley, Jean-Luc Danger:
Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. INDOCRYPT 2011: 22-39 - [c8]Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger:
"Rank Correction": A New Side-Channel Approach for Secret Key Recovery. InfoSecHiComNet 2011: 128-143 - [c7]Nicolas Debande, Youssef Souissi, Maxime Nassar, Sylvain Guilley, Thanh-Ha Le, Jean-Luc Danger:
"Re-synchronization by moments": An efficient solution to align Side-Channel traces. WIFS 2011: 1-6 - [i1]Maxime Nassar, Sylvain Guilley, Jean-Luc Danger:
Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. IACR Cryptol. ePrint Arch. 2011: 534 (2011) - 2010
- [j1]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. 2010: 375245:1-375245:12 (2010) - [c6]Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley:
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE 2010: 849-854 - [c5]Youssef Souissi, Maxime Nassar, Sylvain Guilley, Jean-Luc Danger, Florent Flament:
First Principal Components Analysis: A New Side Channel Distinguisher. ICISC 2010: 407-419
2000 – 2009
- 2009
- [c4]Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar:
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE 2009: 640-645 - [c3]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218 - [c2]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
DPL on Stratix II FPGA: What to Expect?. ReConFig 2009: 243-248 - 2008
- [c1]Sylvain Guilley, Sumanta Chaudhuri
, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong:
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32
Coauthor Index
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